TW508724B - Manufacturing process of hard mark with shallow trench etching of round top corner - Google Patents

Abstract

The present invention provides a shallow trench etching method of hard mark process with round top corner, which comprises the steps of: (1) forming a layer of dielectric film on a semiconductor substrate; (20 spreading a hard mark on the dielectric film, wherein the hard mark is used as a etching mask of dielectric film; (3) then, spreading a photoresist layer on the hard mark, and using traditional exposure and developing technique to define the position of a shallow trench opening in the photoresist layer; (4) using the photoresist layer as an etching mask to perform a first dry anisotropic etching to the hard mark until reaching the upper surface of the dielectric film or base; (5) after etching the hard mark, removing the photoresist layer; (6) applying a first dry isotropic etching by using a first chemical etching mixer as etching plasma and the hard mark as a mask to etch the semiconductor substrate, thereby forming a shallow trench opening with round top corner in the semiconductor substrate and under the hard mark; (7) applying a second dry isotropic etching by a second chemical etching mixer as etching plasma and using the hard mark as a mask to continue etching the semiconductor substrate, thereby completing a shallow trench in the semiconductor substrate.

Description

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V. Description of the invention (1) Field of the invention: The present invention relates to a shallow trench in a semiconductor process, particularly a method using a hard shield with a dome angle. / Re-wood formation method Background of the Invention: With the development of integrated circuit (UC) precision, electronic components have become a trend. By reducing the size of the electronic components, the integration density of the circuit has been increased. However, this has led to difficulties in the two-liter integration process. When the required density of the component is increased, the stability of the microma 2 j increased becomes one of the factors determining the quality yield. The definition of the thin film pattern (Pattern) of the sub-etching technology layer is either being doped. Saying 'each needs to use the lithography process, so we usually need lithography / single engraving times, or The number of masks required is required to indicate the difficulty of this process. From the above, it can be known whether the integration degree of Wang Zhengzhi's photomask industry can go to 0.251 ^ solid semiconductor wide. The lithography and etching process play a pivotal role. The two-color smaller lines are hard. ? First, a cold mask (Hard Mask) and a photosensitive material (Photo-sensitl, coating material) are placed on the Shixi wafer and the dielectric layer film. The collimated light from the light source is illuminated by this layer of photosensitive material after it is covered by glass. Because the light on the reticle, these patterns reflect the incident light, so that the photosensitive material also has the shape of the reticle, so that the photosensitive material on the surface of the wafer can be selectively selected. 508724

In a word, the pattern on the photomask is transferred to the hard mask by the lithography process, and then the final purpose of transferring the entire pattern to the hard mask is achieved by etching. The hard cover layer is used as an etching mask, and the material of the hard cover layer may be selected from SiN, SiON, FLARE, or any combination thereof. ° Let ’s take the first example to illustrate the manufacturing method of shallow trench etching using silicon oxide as the etching mask in the prior art:

Please refer to the first figure (a), a dielectric layer film 12 is attached to a semiconductor substrate 10 to produce an insulating effect, wherein the semiconductor substrate 10 may be _ < 100 > or < 111 > crystal orientation Materials such as single crystal silicon or other semiconductor materials, such as KunAs (GaAs), germanium (Ge), or silicon-on-insulator substrate (Si 1 icon 〇n insulator) and other materials' semiconductor substrate 10 is used to make integrated circuits Various types of active components, passive components, and peripheral circuits, etc. 'Eight films 12 are deposited on a semiconductor substrate by chemical vapor deposition (CVD).

508724 ____ year; month Μ day — V. Description of the invention ⑶ ^ 1 " 10 on top, and the dielectric layer film 12 may be Si02. Please refer to the first figure (b), and then apply the hard shield 16 (hard mark) on the dielectric layer film 12 in order. The materials used for the hard shield 16 are S i 0 N, S i C, S i 3 N 4 and other materials are used as the # 2 engraved mask for the dielectric layer thin film 12 and are deposited and used by Low Pressure CVD and Plasma-Enhanced CVD. The material is silicon nitride. Please refer to the first figure (c), and then apply a shallow trench photoresist layer 18 (shal low trench photoresist 1 ay er) on the hard cover 16 in order and use a conventional exposure and development technology to pattern the photoresist A shallow trench open position 20 is defined, and then the shallow trench photoresist layer 18 is removed. Please refer to the first figure (d), use dry plasma etch to anisotropically (an 丨 s 0 ^ r 〇p 丨 c) the partial etching of the shallow trench opening position 20, Then, the first shallow trench opening 2 2 (partia 1 trench hard mark open) is formed, and in addition to dry plasma etching, ion bombardment and reactive ion etch can be used. Later, when the dielectric layer film was continuously produced using traditional techniques, the following poor quality conditions occurred:

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__material? Fifth, the fifth day of the invention description (4)-(1). Please refer to the first picture (e), if shallow trench photoresist layer 18 and hard cover 16 are used as etching masks to make shallow trenches, and use When dry plasma etching the dielectric layer film 12, although shallow trench openings with dome angles can be formed, different etching speeds are generated due to the different density of the semiconductor circuit patterns, that is, the comparison of the etching speed in areas with lower circuit density. Faster, and the etching speed is slower in areas with higher line density. This is called the load effect (1 oad i ng effect) 0 (2). Please refer to the first figure (f). If only the hard cover 16 is used as the etching cover After the shallow trench is fabricated by the curtain, the dry layer plasma is used to etch the dielectric layer film 12 and the substrate 10, which will cause the problem of lack of dome angles on the upper surface of the semiconductor substrate. All in all, for the production of shallow trenches, it must be achieved that the hard shield 16 has a dome corner and the dielectric film 12 must not have a load effect. Therefore, in response to the above-mentioned adverse phenomena, a shallow trench etch method with a dome angle in a hard shield process has been developed. OBJECTS AND SUMMARY OF THE INVENTION: The purpose of the present invention is to etch shallow trenches with dome angles in the hard shield process, which has the advantages of forming dome angles and reducing the load on the base layer to improve quality and reduce defective rate. The invention comprises the following steps: (1). Forming a semiconductor substrate

508724 ΊΓ ^ \ * 4 / year ^ month / "Xi"!

-: _-_ I ·· ^ rU W V. Description of the invention (5) ------- · Layer dielectric film, in which various active components required for integrated circuits have been fabricated on a semiconductor substrate, For passive components, surrounding circuits, etc., the dielectric layer film is deposited on the semiconductor substrate by chemical vapor deposition. (2) A hard shield is coated on the dielectric layer film, wherein the hard shield is used as an etching mask of the dielectric layer film. (3). The photoresist layer is then coated on the hard cover, and then the photoresist pattern is defined by shallow trench openings using traditional lithographic techniques. (4) The first dry etching is used to etch the opening of the shallow trench in a non-isotropic manner, and the hard shield is engraved and stopped above the dielectric layer film to form a first shallow trench opening. (5) After the hard cover is etched, the photoresist pattern layer is removed in the same process chamber. (6). The hard shield is used as the etching mask and the second dry etching is used to open the first shallow trench to isotropically etch the dielectric layer film and a part of the substrate for use between the semiconductor substrate and the dielectric layer film. The interface forms a round top corner to form a second shallow trench opening. The second dry etching uses hydrogen bromide (HBr) or a carbon-containing gas, for example, CF4, C2F6, CHF3, CH2F2 and other gases are used as the etching agent. (7). The hard shield is used as an etching mask and the third dry etching is used to continue etching the second shallow trench opening to make a third shallow trench opening and maintain the dome angle. The third dry etching uses A specific trench angle and dome angle can be obtained by adjusting the ratio of C 1 2/0 2 mixed gas and pressure. Detailed description of the invention: What is disclosed in the present invention is a method for forming a shallow trench with a dome angle in a hard shield manufacturing process. Now, taking a preferred embodiment as an example, the detailed description is as follows:

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The second figure illustrates the method for forming the hard shallow trench etch of the present invention as follows: 卓 I 転 π has 0; please refer to the second figure (a), a layer 12 of a semiconductor substrate 10 is used to produce Insulation effect, Guang Yue) 丨 < m > or < m> Crystal orientation of single "or other half-bottom is ~ (GaAs), germanium (Ge), or Shi Xi in the insulator-based 'i dagger recorder') Materials, main 1 | ten 1Πα3 seven ilcon on inch bamboo family, Feng V body substrate 1 〇 used to make all kinds of active components, passive components, and peripheral circuits with integrated electrical requirements, dielectric ^ thin film 12 to A chemical vapor deposition (CVD) method is used to deposit a thin film on a semiconductor substrate θ substrate 10 ', and the dielectric layer thin film 12 may be Si02. Please refer to the second figure (b), and then apply a hard mask 16 (hard mark) in order. It is placed on the dielectric layer film 12, where the hard cover 丨 6 is deposited by Low Pressure CVD and Plasmas-Enhanced CVD and the material used is oxynitride -nitride), silicon carbide layer, or silicon nitride layer 0 Please refer to the second figure (c), and then coat the photoresist layer 18 A shallow trench opening 20 is defined in the photoresist layer 18 on the hard cover 16 and using conventional exposure and development techniques.

Page 10 508724 —____—__ j ^ V. Description of the invention (7) · ~~ Factory-__ I * Please refer to the second figure (d), use the first dry etch (anisotropic) Way, the last name is engraved hard cover 1 β and stop until, 12 ^ ^ ^ 10 ^ ^ canal opening 22 'where the first dry anisotropic etching can be plasma etching, ion bombardment (10n bombardment) and reactivity Reactive ion etch method ° Please refer to the second figure (e). After the hard cover is etched, the residual photoresist pattern n is removed in the same process chamber (chamber). 凊 Refer to the second figure (f) 'To form a shallow trench with a dome angle, it must be etched in sections, with a hard shield 16 as the etching mask. First, the second dry pattern is used to etch through the dielectric layer film 12 in an isotropic manner so that the semiconductor substrate at the interface between the semiconductor substrate 10 and the dielectric layer film 12 forms a rounded corner. Among them, the second dry isotropic etching condition uses hydrogen bromide () and carbon contining gas, for example: cf4, C2F6, CHF 3, C Η 2 F 2 and other gases as the etching agent, and hydrogen bromide The ratio to the carbon-containing gas is 20%. The pressure is 20-40mtorr, the RF Powe r is 600-1000W, and the Bias Power is 500-70W. Please refer to the second figure (g), and then use the hard cover 丨 6 as the etching cover. The third dry type # engraving is performed, and the second shallow trench opening 24 is engraved in an anisotropic manner to form the third shallow trench opening 28 and the dome angle is maintained. The second dry anisotropic etching is performed. Conditions using oxygen and silicon etching gas

Amendment 1 Mt; 508724 V. Description of the invention (8) t- (silicon etching gas), for example: C12, HBr and other gases are used as the remaining chemical, and the ratio of oxygen to silicon etching gas is between 7: 1 to 15: 1 room, the pressure is 20-70 mtorr, RF Power is 3 0-5 0 0W, Bias Power is 2 0-3 0 OW, through adjusting the ratio of oxygen and silicon etching gas and pressure to obtain a specific channel Angle (trench angle) and dome angle. An advantage of the present invention is to provide a shallow trench etch with a dome corner in a hard shield process, which is used to form the dome corner and reduce the load of the base layer. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit of the present invention should be considered as The scope of the invention. The scope of protection of the present invention should be determined by the scope of the attached patent application and its equivalent fields.

Page 12 508724 I this / this evening month I more than a simple diagram _% simple diagram without a diagram: Use the following description and the combination of the following diagrams and figures to better understand the content of the present invention and Advantages The first figure (a) is a schematic view of a conventional technique for depositing a dielectric layer on a semiconductor substrate. The first figure (b) is a schematic diagram of a conventional photoresist layer with a hard cover and a trench with an image. The first figure (c) shows the trench opening definition of the trench photoresist layer of the conventional technology. The first figure (d) is a schematic view of a first through hole opening in the conventional technology. The first figure (e) is a schematic view of a loading effect caused by photoresist etching in the conventional technique. The first figure (0 is a schematic diagram of a dome-free corner caused by photoresist-free etching in the conventional technique. The second figure (a) is a schematic diagram of a dielectric layer deposited on a semiconductor substrate according to the present invention. The second figure (b) is the present invention Schematic diagram of trench photoresist layer with hard guard and image. Figure 2 (c) is a schematic diagram of the trench opening defined by the trench photoresist layer of the present invention. Figure 2 (d) is a schematic diagram of the first trench opening of the present invention. The second diagram (e) is a schematic diagram of removing the photoresist layer of the trench according to the present invention. The second diagram (f) is a schematic diagram of the second trench opening of the present invention. The second diagram (g) is a schematic diagram of the third trench opening of the present invention.

508724 Brief description of the drawing, drawing number comparison table ίο- semiconductor; 1 6-hard protection _ 2 0-ditch opening 24-second ditch; ㈣ ?! correction supplement 1 2-dielectric layer thin film layer 1 8-ditch light Barrier position 2 2-first trench opening 2 8-third trench opening

Claims (1)

508724 Sixth, the scope of patent application is that the method of the method is to engraving the shallow corners of the trenches, and the top circle has a band system: Hood: Enclose the paradigm of step-by-step hard line. Please include -φ- τ— • Baoqugou shallow definition; use ->, On the bottom of the base film cover body thin protective layer type semi-electric hard one layer of the film on the thin layer case protection layer of the electric block hard light 1 1 1 into a shaped shape Π the Based on the bottom, the base cover body is guided semi-rigidly or the etched film is thin. The 5 layers are etched with electrical residual dielectric properties. It is not; A blocking agent of light, a mixed base engraving, and a semi-conducting half of this kind of w etch, with the curtain, the engraving as the remaining cover •, the protective layer to the hard case such as the case, the blocking and the light one Divide the first slurry by the electric shift and engraved the bottom cover to protect the shallow corner of the D-channel canal. There is a middle-shaped base with a body-guided stem. Secondly, Shi Hekun ,, / Etching the chemical Uttul species, the second part is engraved to lead half of the moment # continued. Following Zhongzhong 5 The back cover base cover body is the guide cover half i 蒦 ″ one one gukou- > φ and other hard canals ¥ the trench JJ / to shallow, the slurry into electricity more than engraved, as the base 2. If a patent is applied The shallow trench etching method of the first item in the scope, wherein the above semiconductor substrate may be single crystal silicon or other semiconductor materials, such as gallium arsenide (GaAs), germanium (Ge), or silicon-on-insulator substrate (SOI). 3. The shallow trench etching method according to item 1 of the scope of patent application, in which the above-mentioned KI 11111, page 15 508724 6. The scope of patent application The dielectric layer film may be SiO2. 4. For the shallow trench etching method according to item 1 of the patent application, wherein the hard shield is deposited by Low Pressure CVD and Plasma-Enhanced CVD. 5. The shallow trench etching method according to item 1 of the scope of patent application, in which the materials used for the hard shield are Si ON, Si C, Si 3 N 4 and other materials. 6. The shallow trench etching method according to item 1 of the scope of patent application, wherein the first chemical etching mixture mentioned above is hydrogen bromide and carbon-containing gas, and the ratio of the hydrogen bromide to the carbon-containing gas is 20%, Pressure is 20-40 mtorr, RF Power is 600-1000W, Bias Power is 500-70W. 7. The shallow trench etching method according to item 6 of the patent application, wherein the carbon-containing gas of the first chemical etching mixture is CF4, C2F6, CHF3, CH2F: or any combination thereof. 8. The shallow trench etching method according to item 1 of the scope of patent application, wherein the second chemical etching mixture is oxygen and silicon etching gas, and the ratio of the oxygen to the silicon etching gas is 7: 1 to 15: 1, pressure is 20-70mtorr, RF Power is 300-500W, Bias Power is 200-300W. Page 16 508724 VI. Application for patent scope 9. For the shallow trench etching method of the patent application scope item 8, in which the silicon etching gas C 1 2, HBr or any combination thereof of the second chemical etching mixture mentioned above is used. The square corner of the trench is shallow, and the top circle has a protective cover for the Utml species -s'. The steps are listed below. The shallow trench is defined; use a thin protective guide layer on the bottom of the base membrane cover. The semi-electrically hard one is connected to the film and the thin layer. The layer is protected. The electric block is light-hardened one by one. It is formed into a shape. The agent is half-closed to the bottom. The base is mixed with the base. Under the cover body and the guide guide, the guide guide cover is hydrogen-type, semi-semi-hardened, and the type is bromine. The type or type of hardening is the etching of the film, the agent is thin, and the layer is mixed with the curtain. The mask opening etch is etched into the channel erosion. The eclipse trench is oriented in the same direction, the protective layer is shallow and the parallel layer is the wrong type; the case is the hard corner. Block the stem to round one as the engraved one, yes, the first layer Transfer the etched base and mouth resistance to the body; in the opening light, use the conductor to combine the Kun and the etched chemical species, the second type is the tr type, the second is the tr type, and the second is the body type. Gukou Ju = 口 刻 中 # 其 Continue, Following Zhong, the back cover base cover. For the conductor cover, half the gas is protected by the etching method in the hard trench silicon and the trench. With shallow air, the oxygen slurry becomes an electric finish and is etched together. Page 17 508724 VI. Application for patent scope 1 1 · If the shallow trench etching method of the patent application scope item 10, the semiconductor substrate above $ can be monocrystalline silicon or other semiconductor materials, such as > 5 Shenhua at home ( GaAs), germanium (Ge), or silicon-on-insulator substrate (SOI). 1 2. If the shallow trench engraving method is applied for item 10 in the scope of patent application, the above-mentioned dielectric layer film may be SiO 2. 1 3. The shallow trench etching method according to item 10 of the patent application scope, wherein the hard shield is formed by low pressure CVD and plasma enhanced CVD. 1 4 _ The shallow trench etching method as described in item 10 of the scope of patent application, wherein the materials used for the hard cover are Si ON, Si C, Si 3 N 4 and other materials. 15. The shallow trench etch method according to item 10 of the scope of patent application, wherein the carbon-containing gas is CF4, C2F6, CHF3, CH2F2 or any combination thereof. 1 6 _ The shallow trench etching method according to item 10 of the scope of patent application, wherein the above ratio of the hydrogen bromide to the carbon-containing gas is 20%, the pressure is 20-40 mtorr, and the RF Power is 600-1000. W, Bias Power is 500-70W. 1 7. The shallow trench etching method according to item 10 of the scope of patent application, wherein the gas in the rest of Shi Xi is C 1 2, Η B r or any combination thereof. Page 18 508724 6. Application for patent scope 18. For the shallow trench etching method of item 10 of the patent scope, wherein the ratio of the oxygen to the silicon etching gas is 7: 1 to 15: 1, and the pressure is 20 -70mtorr, RF Power is 300-500W, Bias Power is 200-300W ° Page 19