TW416138B - Manufacturing process for notch-free polycide gate of integrated circuit - Google Patents

Abstract

The present invention provides a manufacturing process for notch-free polycide gate of integrated circuit. It is characterized: depositing a layer of rough amorphous silicon film on the silicon dioxide layer on top of polycide gate; using the rough amorphous silicon film surface to scatter the reflection light during the exposure in the microlithography and forming destructive interference to reduce the optical notching of polycide. The major process of the present invention includes the following steps : firstly forming field oxide and gate oxide on the silicon semiconductor substrate; depositing polycide layer, salicide layer, silicon dioxide layer and amorphous silicon layer; then, spraying photoresist on the amorphous silicon layer and using microlithography to create the photoresist pattern; thereafter, using plasma etching technology for anisotropically creating the pattern of the said salicide layer, silicon dioxide layer and amorphous layer simultaneously and followed by using oxide plasma to remove the photoresist; lastly, using the silicon dioxide on top of the said polycide layer as the etching protection layer and using the plasma etching to etch out the polycide layer below the salicide layer; then, completing the manufacturing process for notch-free polycide gate of metal oxide semiconductor transistor.

Description

416138 __ ^ _ V. Description of the Invention (1) (1) Technical Field The present invention discloses a process of a polycide gate (Notched) line with a composite circuit (Integrated Circuit: 1C). This process solves the problem of recession of the complex crystal sand of traditional metal gas semi-transistors (Metal Oxide Semiconductor '; MQS), and we were able to formulate the sub-micron gold gas semi-transistor f. Free line Can. (II) Background of the invention

In the traditional gold gas semi-transistor (MOS) process, when a polycrystalline silicon wafer is formed, a field oxide is first formed, and then a polycrystalline delta layer, a gold vine silicide, and a two-gas-silicon layer are formed. Then, Lithography developed a photoresist pattern. Finally, Plasma Etch technology developed an isotropic-picaJ ly vertical development of the nocturnal sand layer, the golden sanding tree layer and the second Chlorinate the pattern of the 5th layer and spin the 5th layer to remove the photoresist using Qxysen plasraa. However, due to the smooth focus surface caused by the field gasification layer, when the photoresist pattern is formulated, this smooth focus surface The resulting optical reflection effect causes fine recesses in the photoresist pattern of the Ricoh silicon gate to appear, leading to the destruction of gold gas semi-transistors (Fail U (III) Brief description of the invention The main purpose of the present invention is to provide a A recessed integrated circuit polycrystalline silicon wafer manufacturing method. This method first forms a field oxide layer (Gate Oxide) and a gate gasification (Gate Oxide) on a silicon semiconductor substrate. CMS) A4 this 袼 (210x297 mm) —-Ί- -, ------ install ------ order the .f line (please read the note of back cloud; fill in the sheet again) 416138 A7 B7_ Five 'invention description (2), and then deposit the polycrystalline sand layer , Metal sanding waste, second gasification sand layer and amorphous silicon layer (Amorphous Silicon), and then apply f cloth photoresist on the amorphous silicon layer • and use photo-imaging technology to formulate a photoresistance solution, then. The two electric equipment (Plasma Etch) technology simultaneously and unidirectionally formulates the pattern of the metal silicide calendar, dichlorinated sand calendar and amorphous sand layer. The photoresist is removed by oxygen plasma immediately, and finally The silicon dioxide layer above the polycrystalline silicon layer is an Etch Mask. Plasma etching technology is used to remove the polycrystalline silicon layer under the metal silicide layer. It is a kind of polycrystalline sand without depression (Notch ins Free). The fabrication process of the idle gas semi-transistor is completed in 焉. (4) Brief description of the figure. Figure 1 is a cross-sectional view of the process after the completion of the field gasification layer and the idle gasification layer; Process sectional view; FIG. 3 is a sectional view of the cracking process after the metal silicide layer is completed. FIG. 4 is a sectional view of the process after the completion of the second gasified silicon waste. 5 is a cross-sectional view of the process after the amorphous silicon layer is completed. FIG. 6 is a cross-sectional view of the process after the photoresist coating is completed and the photoresist pattern is developed by using photolithography technology; The process cross-section view after the pattern of the metal oxide compound, the second gasification sand layer, and the amorphous sand layer is drawn directionally; FIG. 8 is a process cross-section view after removing the photoresist pattern by using a gas-gas plasma; The mortar etching technology develops the unidirectionality of the crystal paper in a vertical unidirectional manner. The 8S home gradient (CNS) (Π0 × 297 公 * > -4 — I --.------.— install ------ Customized (please read the precautions on the back before filling out this page) __87 _ 416138 A7 V. Description of the invention (]) Process sectional view after 5th night waste. (5) Detailed description of the invention Referring to FIG. 1, firstly, a field gasification layer 12 and an idle gasification® are formed (not shown on the semiconductor silicon substrate 10), and then a® polycrystalline silicon layer 16 is deposited. As shown in FIG. 2 The technique of β formation field gasification primitive 12 is shown in the traditional, .-, equipment

ΤΓII 技 廷. Therefore it will not be described in detail here. For example, B. Davari et al., In IEDM 1983, page 92, proposed shallow trench isolation technology (Shallow Trench Isolation; STI), which uses shallow trenches to form a field gasification box-cage isolation zone. E. Kooi also discloses a selective gasification technology in U.S. Patent No. 3970486. Selectively forms a Mask Asainst Oxidation on the silicon substrate. The thermal growth method forms a two-vaporized silicon film, which is used as the field gasification layer 12, and the electrical components are manufactured on the Shixi substrate in the region of the anti-gasification protective cover; the thickness of the field gasification layer 12 is about 3500 angstroms to 5500 \ Kneading glycosides' pin kneading this easy-change-cost-saving cooperation branch ^ Long

---- 1 I between Egypt. The gate gasification layer is usually formed by thermal gasification, the temperature is between 900X: ~ 1200eC, and the thickness is about 50 ~ 200 angstroms. (Low Pres-surs Chemica 1 Vapor Deposition; LPCVD) is formed by the in-situ hybrid deposition method. The reaction gas is a mixed gas of 15% PH5 and 85% SiH4 and 5% L at a temperature of 570X; In order to dope impurity atoms such as dish atoms, and 5% PH ”and 95% in the mixed gas, the purpose is to precisely adjust the uniformity of the indirect impurity concentration of the wafer, and its thickness is between 500 and 2000 Angstroms. Referring now to FIG. 3, a layer of metal sand 18 is formed in a thickness of between 500 and 1500 angstroms. This layer is usually a sandpaper formed by CVD. ΙΙΛΑ is used in a 4-shaped Uiox. 297mm) ~ 416138 7 A7 B7 V. Description of the invention (4) Chemical conversion and casting (Tungsten silicide VS〗 〖x), using Genus 8500 deposition equipment as an example, the reaction gas is 6 and 5 ["4, can form two Siliconized WSU. Next, a dichlorinated sand layer 20 is formed, as shown in FIG. 4. The two-gasification sand layer 20 is usually formed by a Low Pressure Chemical Vapor Deposition (LPCVD) method. The reaction gases are Si (CH3) 4_, NjQ, and 0; _, the temperature is 7203C, and the reaction power is 200. ~ 300 mTo ". The thickness is between 500 and 1500 Angstroms. Next, a thick: intercalated amorphous silicon layer 22 is formed, as shown in Figure 5. The layer 22 is usually formed by CVD, and the reaction gas is SiHt. The flow is 350 seem, the temperature is 570 ° C, the reaction history is 0.1 ~ 0.3Torr, and the thickness is about 300 ~ 1000 angstroms. Next, a coating of photoresist 24 is formed, as shown in FIG. The traditional photolithographic technique is used to formulate the photoresist 24 pattern, as shown in Fig. 6. Then, the metal sanding compound is formed using plasma etching technology or activated ion engraving technology. The patterns of the sand layer 20 and the amorphous sand layer 22 are shown in Fig. 7. Taking the RAINBOW 442S mold peeking and engraving machine produced by the American company Lam Resea-rch as an example, the reaction gas is Cb 420 seem, HBr 80 seem, In He 160 seem, the unique effect of the metal silicide layer 13 can achieve the effect of vertical orientation. As an example, the RAIN-B0W4520 plasma winning engraving machine produced by LamResearch Co., Ltd. is set to engraving chopsticks with a reaction chamber power of 250 mTorr and RF power of 300 watts. Reaction gas flow Ar350 seem N CF4 20sccnu CHF3 20 seem. The etched rate of the vaporized silicon layer 20 is about 2500 angstroms / tain, and it can achieve the vertical unidirectional etching effect. Then use the gas-gas slurry to remove the photoresist on the paper scale. Use Linguojiajia # 车(CNS) A4 specification (210X297 mm) -6 — (Please read the note on the back and fill in the difference I) Binding it 416138 V. Description of the invention (5) 24, as shown in Figure 8. Finally, The silicon dioxide layer 20 above the polycrystalline silicon layer 16 is used as an etching protection mask (Etch Mask), and the exposed polycrystalline silicon layer 16 and the amorphous silicon layer are etched by plasma uranium etching technology or activated ion etching. 22 and a part of the dioxide layer 20, leaving the part of the polycrystalline silicon gate, as shown in Figure 9, a notching free (notching free) polycrystalline silicon metal oxide semiconductor semi-transistor manufacturing process was completed in Lam. Lam, USA As an example, the RAINBOW 4400 electro-etching machine manufactured by Research Company is set to an inverse etching condition. When the chamber pressure is 525 mTorr, RF power is 450 watts, and the flow rate of the reaction gas is He 18〇cm, cl2 420 seem, Hbr 80sccm, the saturation rate of the polycrystalline sand layer 16 is about 3800 angstroms / min, and it can achieve vertical unidirectional Etching effect. ^ (Please read the note on the back first and fill in 夂 " >

T paper method scale uses China's "Home Dynasty t standard (CNS > A4 size (210X297 cm ^) -7

Claims (1)

416138 C8 VI. Application for patent scope 1. A recessed integrated circuit polycrystalline silicon idle process, pseudo-comprising: Selective topography or field isolation region on a semiconductor substrate, leaving the element area of the field effect device to be produced Forming a dynode dielectric layer on the substrate of the element region; depositing a layer of polycrystalline sand waste on the element region and the field isolation region; forming a layer of metal on the surface of the polycrystalline sand layer Sanding material; forming a silicon dioxide layer on the surface of the metal sanding material®; forming an amorphous silicon layer on the surface of the silicon dioxide layer; the amorphous silicon layer is 540 ~ 600 ° by LPCVD method C is completed; selectively removing part of the amorphous silicon layer, silicon dioxide layer, and metal silicide layer, leaving a portion of the polycrystalline silicon gate to be fabricated; and vertically etching the polycrystalline silicon layer And the amorphous silicon layer and part of the sand dioxide layer 'leave the part of the complex crystalline silicon gate 2- as described in the process of claim 1 in the patent process, wherein the amorphous sand is selectively removed Steps to equal layers include: Said layer of amorphous silicon is formed on the photoresist; using a photoresist pattern developed the technique of Toru Movies; engraved the name of the amorphous sand, sand and two vaporized metal silicide ®; the removal of the photoresist. 3. The process according to item 2 of the patent application, wherein the unique engraving is vertical plasma etching or activated ion etching. 4. The process according to item 1 of the patent application scope, wherein the method for forming the field separation region is to thermally grow a thick silicon dichloride layer. The paper standard is selected in the aa home standard (CNS) A4 specification (210X 297 male ¢) ------- ^ ------------------------- -(Please read the idea on the back of the book before writing the page) 416138 βλ Cq 6. Application for patent scope 5. For the process of applying for the scope of item 1 of the patent scope, the thickness of the polycrystalline silicon layer is between 1500 and Between 3000 Angstroms. 6. The process of claim 1, wherein the thickness of the metal silicide layer is between 500 and 2000 angstroms. 7. The process of claim 1 in which the thickness of the amorphous silicon layer is about 300 to 1000 angstroms. (Please read the δ..VJ notice before filling out this page.) This paper size is in Chinese painter's mark (CNS) A4 specification (210X 297 mm)