WO2022198949A1 - 半导体结构的制作方法 - Google Patents

半导体结构的制作方法 Download PDF

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Publication number
WO2022198949A1
WO2022198949A1 PCT/CN2021/120321 CN2021120321W WO2022198949A1 WO 2022198949 A1 WO2022198949 A1 WO 2022198949A1 CN 2021120321 W CN2021120321 W CN 2021120321W WO 2022198949 A1 WO2022198949 A1 WO 2022198949A1
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Prior art keywords
layer
dielectric
sacrificial
semiconductor structure
fabricating
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PCT/CN2021/120321
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English (en)
French (fr)
Inventor
宛强
夏军
占康澍
李森
徐朋辉
刘涛
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长鑫存储技术有限公司
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Priority to US17/648,582 priority Critical patent/US20220310402A1/en
Publication of WO2022198949A1 publication Critical patent/WO2022198949A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Definitions

  • the embodiments of the present application relate to, but are not limited to, a method for fabricating a semiconductor structure.
  • the dry etching process and the wet etching process can be selected according to actual needs.
  • the dry etching process mainly uses reactive gas and plasma etching to remove materials in specific areas.
  • the wet etching process It mainly uses chemical reagents to react with the material to be etched to remove specific exposed materials. Compared with the dry etching process, the wet etching process has a higher etching selectivity ratio.
  • the target pattern is obtained by the dry etching process and the wet etching process, due to the problem of the etching selectivity ratio of different materials, the morphology of the final obtained target pattern is often abnormal.
  • embodiments of the present application provide a method for fabricating a semiconductor structure, including: providing a substrate; forming an insulating layer on the substrate, the insulating layer including a first dielectric layer and a second dielectric layer; wherein , the insulating layer has a first trench, the second dielectric layer covers the upper surface of the first dielectric layer; a protective layer is formed, the protective layer covers the upper surface of the second dielectric layer, the first dielectric layer The bottom and sidewalls of a trench; part of the protective layer is removed to expose at least part of the surface of the second dielectric layer; the second dielectric layer is removed by a first wet etching process, and the first wet etching process is used to remove the second dielectric layer.
  • the second wet etching process has a first etching selectivity ratio for the material of the second dielectric layer and the material of the first dielectric layer; the protective layer is removed by a second wet etching process, and the second wet etching process is used to remove the protective layer.
  • the etching process has a second etching selectivity ratio for the material of the protective layer and the material of the first dielectric layer, and the second etching selectivity ratio is greater than the first etching selectivity ratio.
  • 1 to 7 are schematic structural diagrams corresponding to each step of a method for fabricating a semiconductor structure
  • FIGS. 8 to 17 are schematic structural diagrams corresponding to each step of the method for fabricating a semiconductor structure according to an embodiment of the present application.
  • a substrate 10 a substrate 10, a first dielectric material layer 11a, a first sacrificial material layer 12, and a photoresist layer 13 are provided which are sequentially stacked, and the photoresist layer 13 has an opening pattern.
  • the first sacrificial material layer 12 is a multi-layer structure.
  • the first sacrificial material layer 12 includes a first sacrificial sub-layer 121 and a second sacrificial sub-layer 122 arranged in layers, and the first sacrificial sub-layer 121 is located in the first sacrificial sub-layer 121.
  • the material of the second sacrificial sub-layer 122 is the same as the material of the first dielectric material layer 11a.
  • the photoresist layer 13 (refer to FIG. 1 ) as a mask, part of the first sacrificial material layer 12 (refer to FIG. 1 ) is removed by etching, and the remaining first sacrificial material layer 12 is used as the first sacrificial layer 12 a , the first sacrificial layer 12a has a second groove 12b; after the first sacrificial layer 12a is formed, the photoresist layer 13 is removed.
  • a second dielectric material layer 14a is formed, and the second dielectric material layer 14a covers the upper surface of the first sacrificial layer 12a, the bottom and the sidewalls of the second groove 12b.
  • the sidewalls of the second groove 12b correspond to the sidewalls of the first sacrificial layer 12a.
  • the second dielectric material layer 14a (refer to FIG. 3 ) located on the upper surface of the first sacrificial layer 12a is removed, and the second dielectric material layer 14a located at the bottom of the second groove 12b is removed, leaving the first sacrificial layer 12a
  • the second dielectric material layer 14a on the sidewall, and the remaining second dielectric material layer 14a is used as the second dielectric layer 14 .
  • the first sacrificial layer 12a is removed.
  • the first sacrificial layer 12a can only be removed by a dry etching process, and the etching selection of the dry etching process is relatively small.
  • the exposed surface of the first dielectric material layer 11a will be over-etched, and the "exposed surface” includes the surface in contact with the first sacrificial layer 12a, and includes the first On the surface of the sacrificial layer 12a and the second dielectric layer 14 exposed together, the degree of over-etching is related to the exposure time, and the longer the exposure time is, the higher the degree of over-etching is.
  • the exposed first dielectric material layer 11 a (refer to FIG. 5 ) of the second dielectric layer 14 is removed, and the remaining first dielectric material layer 11 a constitutes the first dielectric layer 11 .
  • part of the first dielectric material layer 11a is removed by etching, leaving the first dielectric material layer 11a between the second dielectric layer 14 and the substrate 10 to form the first dielectric layer 11.
  • the two dielectric layers 14 expose the sidewall surfaces of the first dielectric layer 11 .
  • the second dielectric layer 14 is removed by a wet etching process (refer to FIG. 6 ).
  • the wet etching process has an etching selectivity ratio for the material of the second dielectric layer 14 and the material of the first dielectric layer 11. The smaller the etching selectivity ratio, the higher the surface roughness of the sidewall of the first dielectric layer 11. In severe cases , which may generate defects such as burrs and affect the performance of the semiconductor structure.
  • the material of the second dielectric layer 14 is silicon dioxide
  • the material of the first dielectric layer 11 is silicon oxynitride
  • the etchant of the wet etching process is ammonium hydrogen fluoride solution. 14
  • the first dielectric layer 11 will also be etched, so that the sidewall of the first dielectric layer 11 is formed with defects such as burrs.
  • FIGS. 8 to 17 are schematic structural diagrams corresponding to each step of the method for fabricating a semiconductor structure according to an embodiment of the present application.
  • the fabrication method of the semiconductor structure includes the following steps:
  • a substrate 20, a first dielectric material layer 21a, a first sacrificial material layer 22, and a photoresist layer 23 are provided which are sequentially stacked, and the photoresist layer 23 has an opening pattern.
  • the first sacrificial material layer 22 includes a first sacrificial sub-layer 221 and a second sacrificial sub-layer 222 arranged in layers, and the first sacrificial sub-layer 221 is located between the first dielectric material layer 21a and the second sacrificial sub-layer 222;
  • a sacrificial material layer 22 may contain the material of the first dielectric material layer 21a, for example, the material type of the second sacrificial sub-layer 222 is the same as that of the first dielectric material layer 21a.
  • the atomic ratio of the material of the second sacrificial sub-layer 222 is adjusted, or the material of the first dielectric material is adjusted.
  • the atomic ratio of the material of the layer 21a changes the material properties of the second sacrificial sublayer 222 or the first dielectric material layer 21a, so that the etchant has a difference between the material of the second sacrificial sublayer 222 and the material of the first dielectric material 21a.
  • the etching selectivity ratio is greater than 1, thereby reducing damage to the first dielectric material layer 21a caused by the subsequent etching process of removing the second sacrificial sublayer 222 .
  • the material of the second sacrificial sub-layer 222 is the first silicon oxynitride
  • the material of the first dielectric material layer 21a is the second silicon oxynitride, both of which are silicon oxynitride materials, and the second silicon oxynitride
  • concentration of silicon atoms in the first silicon oxynitride is greater than that in the first silicon oxynitride
  • the hardness of the second silicon oxynitride is greater than that of the first silicon oxynitride.
  • the silicon oxynitride material is selected as the second sacrificial sublayer 222, mainly to prevent the sawtooth standing wave effect from being generated when the resist layer 23 is formed by photolithography, thereby affecting the shape of the semiconductor device finally formed; at the same time, nitrogen Compared with the photoresist material (that is, the material of the photoresist layer 23 ), the silicon oxide material has higher hardness and can be used as a hard mask layer to avoid the etching of the photoresist material by the etchant and affect the accuracy of the opening pattern, so as to ensure the first The positional accuracy of a sacrificial material layer 22 meets a preset requirement.
  • the material of the first sacrificial sub-layer 221 is carbon or carbon-containing organic compounds
  • the carbon-containing organic compounds include resin compounds
  • the first sacrificial sub-layer 221 can be removed by an ashing process, which is beneficial to avoid the first sacrificial sub-layer 221 The removal process causes damage to the first dielectric material layer 21a to ensure that the first dielectric material layer 21a has good material properties.
  • the above-mentioned materials of the first sacrificial sub-layer 221 and the removal process of the first sacrificial sub-layer 221 are only illustrative.
  • the photoresist layer 23 (refer to FIG. 8 ) as a mask, part of the first sacrificial material layer 22 (refer to FIG. 8 ) is removed by etching, and the remaining first sacrificial material layer 22 is used as the first sacrificial layer 22 a , the first sacrificial layer 22a has a second groove 22b; after the first sacrificial layer 22a is formed, the photoresist layer 23 is removed.
  • the photoresist layer 23 is used as a mask to sequentially etch the first sacrificial sublayer 221 and the second sacrificial sublayer 222 to form a second groove 22b exposing the first dielectric material layer 21a. After the two grooves 22b, the photoresist layer 23 is removed, so that the first sacrificial sub-layer 221 and the second sacrificial sub-layer 222 can be etched in the same process step, which reduces the etching steps and reduces the process cost.
  • the second sacrificial sublayer is first etched to form an opening pattern exposing the top surface of the first sacrificial sublayer; after part of the second sacrificial sublayer is etched, the photolithography is removed adhesive layer; after removing the photoresist layer, using the remaining second sacrificial sub-layer with the opening pattern as a mask, etching the first sacrificial sub-layer to form a second groove.
  • the removal process of the photoresist layer is beneficial to cause damage to the first dielectric material layer, and the damage includes but is not limited to changing the topographical features of the first dielectric material layer and changing the material properties of the first dielectric material layer.
  • the etchant for etching the first sacrificial sub-layer 221 and the second sacrificial sub-layer 222 may be the same etchant or different etchants.
  • the material of the first dielectric material layer 21a and the material of the second sacrificial sub-layer 22 belong to the same type. By adjusting the atomic ratio of the material of the first dielectric material layer 21a, the first dielectric material layer 21a is enlarged.
  • the gap between the first sacrificial sublayer 221 and the second sacrificial sublayer 222 is narrowed Therefore, the first sacrificial sub-layer 221 and the second sacrificial sub-layer 222 are finally etched by the same etchant, and the etchant will not cause damage to the first dielectric material layer 21a. In this way, it is beneficial to reduce the etching process and reduce the process cost.
  • a second dielectric material layer 24a is formed, the second dielectric material layer 24a covers the upper surface of the first sacrificial layer 22a, the bottom and sidewalls of the second groove 22b, and the sidewall of the second groove 22b is equivalent to the first sidewalls of the sacrificial layer 22a.
  • the atomic layer deposition process is used to form the second dielectric material layer 24a, so that the thickness of the second dielectric material layer 24a precisely meets the preset requirements, so that the second dielectric layer formed by etching the second dielectric material layer 24a It has high positional accuracy, so that the first dielectric layer formed by using the second dielectric layer as a mask etching has high positional accuracy; in addition, using the atomic layer deposition process to form the second dielectric material layer 24a
  • the second dielectric material layer 24a has high density, that is, the second dielectric material layer 24a has high structural strength, so as to avoid the collapse of the second dielectric material layer due to the loose structure.
  • the material of the second dielectric material layer 24a is silicon dioxide, and the price of the silicon dioxide material is low, which is beneficial to reduce the manufacturing cost of the semiconductor structure;
  • the speed of the silicon oxide material is faster, which is beneficial to shorten the process time.
  • a first dielectric layer 21 and a second dielectric layer 24 are formed.
  • the second dielectric material layer 24a (refer to FIG. 10) is etched by a maskless dry etching process, and the upper surface of the first sacrificial layer 22a and the bottom of the second groove 22b are removed.
  • the second dielectric material layer 24a is removed, and the first sacrificial layer 22a is removed, and the remaining second dielectric material layer 24a constitutes the second dielectric layer 24 .
  • the first dielectric material layer 21a (refer to FIG. 10 ) is etched, the first dielectric material layer 21a exposed by the second dielectric layer 24 is removed, and the remaining first dielectric material layer 21a constitutes the first dielectric Layer 21, the second dielectric layer 24 covers the upper surface of the first dielectric layer 21, the first dielectric layer 21 and the second dielectric layer 24 constitute an insulating layer (not shown), and the insulating layer has a first groove 24b.
  • top surface and sidewall surface of the finally formed second dielectric layer 24 are curved surfaces rather than flat surfaces, the top width of the finally formed second dielectric layer 24 is smaller than the bottom width, and the bottom surface width of the second dielectric layer 24 is equal to The width of the top surface of the first dielectric layer 21 .
  • a protective layer 25 is formed.
  • a deposition process is used to form the protective layer 25, and the protective layer 25 covers the upper surface of the second dielectric layer 24, the bottom and sidewalls of the first trench 24b, in other words, the protective layer 25 covers the substrate 20, the first trench 24b A dielectric layer 21 and exposed surfaces of the second dielectric layer 24 .
  • the hardness of the material of the protective layer 25 is greater than the hardness of the material of the second dielectric layer 24 , for example, the material of the protective layer 25 is silicon nitride.
  • Silicon nitride has the characteristics of high hardness and low cost. Due to the high hardness of silicon nitride, the thickness of the protective layer 25 can be thinner, and there is no need to worry about the problem of collapse due to insufficient structural strength, and the thickness of the protective layer 25 is relatively thin.
  • the thickness of the layer 25 is relatively thin, which is beneficial to shorten the deposition and formation time of the protective layer 25 and further shorten the fabrication time of the semiconductor structure; in addition, the thickness of the protective layer 25 is relatively thin, and the material price of the protective layer 25 is low, both of which are It is beneficial to reduce the fabrication cost of the semiconductor structure.
  • the protective layer 25 can be formed by the atomic layer deposition process. Since the atomic layer deposition process is layer-by-layer deposition, the distance between adjacent atoms or molecules is small. Therefore, the protective layer 25 formed by the atomic layer deposition process It has a large contact area with the surfaces of the first dielectric layer 21 and the second dielectric layer 24, and the bonding strength is high. Before the material of the protective layer 25 is cured, the material of the protective layer 25 can better adhere to the first medium. The surfaces of the layer 21 and the second dielectric layer 24 ensure the effective formation of the protective layer 25 .
  • the curing of the material of the protective layer 25 means that the material of the protective layer 25 exhibits a certain fluidity during the deposition process, or in other words, the particles of the material of the protective layer 25 are small, and the material of the protective layer 25 is deposited on the first medium. After the surfaces of the layer 21 and the second dielectric layer 24 are cured, they need to be cured by heating or other methods to ensure that the protective layer 25 has high structural strength.
  • At least one side surface of the second dielectric layer 24 is a curved surface rather than a vertical plane, which is beneficial to improve the effective adhesion rate of the material of the protective layer 25, prevent the material of the protective layer 25 from collapsing or slipping due to insufficient adhesion strength, and ensure the protective layer 25. 25 effective formation.
  • the thickness of the protective layer 25 is 5-10 nm, for example, 7 nm, 8 nm or 9 nm.
  • the thickness of the protective layer 25 is too thick, the deposition time is long, and raw materials are wasted; if the thickness of the protective layer 25 is too thin, the structural strength of the protective layer 25 is low, and collapse is likely to occur, and the protective effect is weak, which may be in the second dielectric layer.
  • the removal process of 24 is removed or etched through, thereby exposing the sidewall of the first dielectric layer 21 , causing the sidewall of the first dielectric layer 21 to be damaged by the etchant of the second dielectric layer 24 .
  • a second sacrificial layer 26 is formed.
  • a second sacrificial layer 26 is formed before removing part of the protective layer 25 to expose the second dielectric layer 24 .
  • the second sacrificial layer 26 fills the first trench (not shown) and covers the exposed surface of the protective layer 25 , the setting of the second sacrificial layer 26 enables subsequent etching of the protective layer 25 through a maskless dry etching process to expose the surface of the second dielectric layer 24 without providing an additional mask for selective dry etching
  • the etching process is beneficial to reduce the process cost; in addition, through the setting of the second sacrificial layer 26, when the protective layer 25 is etched by the dry etching process, the insulating layer (not marked) is not easy to fall, which ensures the stability of the semiconductor structure. sex.
  • part of the protective layer is removed to expose at least part of the surface of the second dielectric layer.
  • the hardness of the material of the second sacrificial layer 26 is lower than the hardness of the material of the second dielectric layer 24 .
  • the material of the second sacrificial layer 26 is carbon or carbon-containing organic compounds.
  • the second sacrificial layer 26 may be Removal by ashing process is beneficial to avoid damage to the protective layer 25 and damage to the first dielectric layer 21 by the removal process of the second sacrificial layer 26 , so as to ensure that the first dielectric layer 21 has good structural characteristics.
  • the use of a planarization process to grind and etch the protective layer 25 may contaminate other adjacent structures. This is because carbon or carbon-containing organic substances are soft in texture and have a certain fluidity. If a planarization process is used to grind and etch the protective layer 25, part of the material of the second sacrificial layer 26 may be thrown out during the grinding process, causing splashing. radiation pollution.
  • part of the protective layer 25 is removed.
  • the second dielectric layer 24 , the protective layer 25 and the second sacrificial layer 26 are etched by a maskless dry etching process, and part of the second dielectric layer 24 is removed.
  • the upper surface of the remaining protective layer 25 is flush with the upper surface of the remaining second dielectric layer 24, that is, the protective layer 25 exposes the upper surface of the second dielectric layer 24;
  • the carbon compound has a soft texture and is easy to remove. Therefore, the upper surface of the remaining second sacrificial layer 26 is lower than the upper surface of the remaining protective layer 25 .
  • the remaining second sacrificial layer 26 (refer to FIG. 14) is removed.
  • an ashing process is used to remove the remaining second sacrificial layer 26.
  • the second dielectric layer 24 plays a protective role and an isolation role to prevent the ashing process from affecting the second sacrificial layer 26.
  • the top surface of a dielectric layer 21 is damaged, and impurities formed by the ashing process are prevented from adhering to the top surface of the first dielectric layer 21, so as to ensure that the first dielectric layer 21 has good characteristics.
  • the second dielectric layer 24 is removed by a first wet etching process.
  • the first etching selection ratio of the first wet etching process to the material of the second dielectric layer 24 and the material of the first dielectric layer 21 is 5:1 to 10:1, for example, 6:1, 7 : 1 or 8: 1; wherein, the etching solution used in the first wet etching process includes an ammonium bifluoride solution.
  • the ammonium bifluoride solution is generally a mixed solution of ammonium fluoride and a diluted hydrogen fluoride solution, and the mixed solution is generally used to etch and remove the silicon dioxide solution.
  • the first wet etching process can be performed at a lower ambient temperature, for example, below 150°C.
  • the protective layer 25 is removed by a second wet etching process (refer to 16).
  • the second wet etching process has a second etching selectivity ratio between the material of the protective layer 25 and the material of the first dielectric layer 21, in order to reduce the damage to the sidewall of the first dielectric layer 21 caused by the etching process , the second etching selection ratio should be greater than the first etching selection ratio; in some embodiments, the second etching selection ratio can be set to be 2 to 8 times the first etching selection ratio, such as 3 times, 5 times or 7 times, thereby ensuring that the sidewall surface of the first dielectric layer 21 is a relatively smooth surface.
  • the ratio of the second etching selection ratio to the first etching selection ratio is set too high, the etching rate of the protective layer 25 may be slow and the process time may be longer; if the ratio is too small, the The improvement of the structural characteristics of the sidewall of the first dielectric layer 21 is weak, and the preset improvement effect cannot be achieved.
  • the etching selection ratio of the second wet etching process to the material of the protective layer 25 and the material of the first dielectric layer 21 is 20:1 ⁇ 40:1, such as 25:1, 30:1 or 35 : 1; wherein, the etching solution used in the second wet etching process includes a phosphoric acid solution.
  • Phosphoric acid solution is generally used as an etching solution for silicon nitride solution, which can remove silicon nitride film well, and has little damage to silicon oxide film.
  • the second wet etching process can be performed at a lower ambient temperature, for example, below 150°C.
  • a protective layer is used to cover the sidewall of the first dielectric layer to avoid damage to the sidewall of the first dielectric layer caused by the first wet etching process; at the same time, a second The etching selectivity ratio is greater than the first etching selectivity ratio, so that the damage to the surface of the first dielectric layer caused by the second wet etching process is reduced, so that the first dielectric layer has good structural characteristics.

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Abstract

本申请实施例提供一种半导体结构的制作方法，包括：提供衬底；于衬底上形成绝缘层，绝缘层包括第一介质层和第二介质层；其中，绝缘层具有第一沟槽，第二介质层覆盖第一介质层的上表面；形成保护层，保护层覆盖第二介质层的上表面、第一沟槽的底部及侧壁；去除部分保护层，以暴露第二介质层的至少部分表面；采用第一湿法刻蚀工艺去除第二介质层，第一湿法刻蚀工艺对第二介质层的材料和第一介质层的材料具有第一刻蚀选择比；采用第二湿法刻蚀工艺去除保护层，第二湿法刻蚀工艺对保护层的材料和第一介质层的材料具有第二刻蚀选择比，第二刻蚀选择比大于第一刻蚀选择比。

Description

半导体结构的制作方法
交叉引用
本申请要求于2021年3月25日递交的名称为“半导体结构的制作方法”、申请号为202110320475.9的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及但不限于一种半导体结构的制作方法。
背景技术
在半导体结构的制作过程中，可以根据实际需要选择干法刻蚀工艺和湿法刻蚀工艺，干法刻蚀工艺主要利用反应气体与等离子体刻蚀去除特定区域的材料，湿法刻蚀工艺主要利用化学试剂与被刻蚀材料发生反应刻蚀去除暴露的特定材料，相对于干法刻蚀工艺，湿法刻蚀工艺具有较高的刻蚀选择比。在实际工艺中，在利用干法刻蚀工艺和湿法刻蚀工艺获取目标图案时，由于不同材料的刻蚀选择比的问题，经常会导致最终获取的目标图案的形貌出现异常。
发明内容
为解决上述问题，本申请实施例提供一种半导体结构的制作方法，包括：提供衬底；于所述衬底上形成绝缘层，所述绝缘层包括第一介质层和第二介质层；其中，所述绝缘层具有第一沟槽，所述第二介质层覆盖所述第一介质层的上表面；形成保护层，所述保护层覆盖所述第二介质层的上表面、所述第一沟槽的底部及侧壁；去除部分所述保护层，以暴露所述第二介质层的至少部分表面；采用第一湿法刻蚀工艺去除所述第二介质层，所述第一湿法刻蚀工艺对所述第二介质层的材料和所述第一介质层的材料具有第一刻蚀选择比；采用第二湿法刻蚀工艺去除所述保护层，所述第二湿法刻蚀工艺对所述保护层的材料和所述第一介质层的材料具有第二刻蚀选择比，所述第二刻蚀选择比大于所述第一刻蚀选择比。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非 有特别申明，附图中的图不构成比例限制。
图1至图7为半导体结构的制作方法各步骤对应的结构示意图；
图8至图17为本申请实施例提供的半导体结构的制作方法各步骤对应的结构示意图。
具体实施方式
参考图1，提供依次堆叠的衬底10、第一介质材料层11a、第一牺牲材料层12以及光刻胶层13，光刻胶层13具有开口图案。
第一牺牲材料层12为多层结构，在一些实施例中，第一牺牲材料层12包括层叠设置的第一牺牲子层121和第二牺牲子层122，第一牺牲子层121位于第一介质材料层11a和第二牺牲子层122之间，第二牺牲子层122的材料与第一介质材料层11a的材料相同。
参考图2，以光刻胶层13(参考图1)为掩膜，刻蚀去除部分所述第一牺牲材料层12(参考图1)，剩余第一牺牲材料层12作为第一牺牲层12a，第一牺牲层12a具有第二凹槽12b；在形成第一牺牲层12a之后，去除光刻胶层13。
参考图3，形成第二介质材料层14a，第二介质材料层14a覆盖第一牺牲层12a的上表面、第二凹槽12b的底部及侧壁。第二凹槽12b侧壁相当于第一牺牲层12a侧壁。
参考图4，去除位于第一牺牲层12a上表面的第二介质材料层14a(参考图3)，以及去除位于第二凹槽12b底部的第二介质材料层14a，保留位于第一牺牲层12a侧壁的第二介质材料层14a，剩余第二介质材料层14a作为第二介质层14。
参考图5，去除第一牺牲层12a。
由于第二牺牲子层122的材料与第一介质材料层11a的材料相同，因此，只能采用干法刻蚀工艺去除第一牺牲层12a，而由于干法刻蚀工艺的刻蚀选择比较小，在干法刻蚀工艺的刻蚀过程中，第一介质材料层11a被暴露的表面会受到过刻蚀，“被暴露的表面”包括与第一牺牲层12a接触的表面，以及包括第一牺牲层12a和第二介质层14共同暴露的表面，过刻蚀程度与暴露时间有关，暴露时间越长，过刻蚀程度越高。
参考图6，去除第二介质层14暴露的第一介质材料层11a(参考图5)，剩余第一介质材料层11a构成第一介质层11。
利用第二介质层14作为掩膜，刻蚀去除部分第一介质材料层11a，保留位于第二介质层14和衬底10之间的第一介质材料层11a，形成第一介质层11，第二介质层14暴露第一介质层11侧壁表面。
参考图7，采用湿法刻蚀工艺去除第二介质层14(参考图6)。
由于第二介质层14暴露第一介质层11侧壁表面，因此，在去除第二介质层14的湿法刻蚀工艺过程中，湿法刻蚀工艺的刻蚀剂会与第一介质层11侧壁表面接触，从而对第一介质层11侧壁表面造成损伤。湿法刻蚀工艺对第二介质层14的材料和第一介质层11的材料具有刻蚀选择比，刻蚀选择比越小，第一介质层11侧壁表面粗糙度越高，严重情况下，可能生成毛刺等缺陷，影响半导体结构的性能。
在一些实施例中，第二介质层14的材料为二氧化硅，第一介质层11的材料为氮氧化硅，湿法刻蚀工艺的刻蚀剂为氟化氢铵溶液，在去除第二介质层14的同时，对第一介质层11也会有刻蚀，从而使第一介质层11侧壁形成有毛刺等缺陷。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图8至图17为本申请实施例提供的半导体结构的制作方法各步骤对应的结构示意图。半导体结构的制作方法包括以下步骤：
参考图8，提供依次堆叠的衬底20、第一介质材料层21a、第一牺牲材料层22以及光刻胶层23，光刻胶层23具有开口图案。
第一牺牲材料层22包括层叠设置的第一牺牲子层221和第二牺牲子层222，第一牺牲子层221位于第一介质材料层21a和第二牺牲子层222之间；其中，第一牺牲材料层22可以包含第一介质材料层21a的材料，示例性地，第二 牺牲子层222的材料类型与第一介质材料层21a的材料类型相同。
在一些实施例中，在不改变第二牺牲子层222和第一介质材料层21a的材料类型的情况下，调整第二牺牲子层222的材料的原子数占比，或者调整第一介质材料层21a的材料的原子数占比，改变第二牺牲子层222或第一介质材料层21a的材料特性，使得刻蚀剂对第二牺牲子层222的材料与第一介质材料21a的材料的刻蚀选择比大于1，从而减轻后续去除第二牺牲子层222的刻蚀工艺对第一介质材料层21a造成的损伤。
在一些实施例中，第二牺牲子层222的材料为第一氮氧化硅，第一介质材料层21a的材料为第二氮氧化硅，两者同属氮氧化硅材料，第二氮氧化硅中的硅原子浓度大于第一氮氧化硅中的硅原子浓度，第二氮氧化硅的硬度大于第一氮氧化硅的硬度。其中，选用氮氧化硅材料作为第二牺牲子层222，主要是为了防止利用光刻技术形成刻胶层23时产生锯齿状驻波效应，进而影响最终形成的半导体器件的形貌；同时，氮氧化硅材料相对于光阻材料(即光刻胶层23的材料)具有较高的硬度，可作为硬掩模层存在，避免刻蚀剂刻蚀光阻材料而影响开口图案的精度，保证第一牺牲材料层22的位置精度满足预设要求。
此外，第一牺牲子层221的材料为碳或含碳有机物，含碳有机物包括树脂类化合物，第一牺牲子层221可通过灰化工艺去除，如此，有利于避免第一牺牲子层221的去除工艺对第一介质材料层21a造成损伤，保证第一介质材料层21a具有良好的材料特性。
需要说明的是，上述第一牺牲子层221的材料以及第一牺牲子层221的去除工艺仅是示例性说明，在实际工艺生产过程中，可通过调整第一牺牲子层221的材料和第一牺牲子层221的去除工艺，避免去除工艺引入的成分与第一介质材料层21a发生反应或者对第一介质材料层21a造成轰击损伤，从而保证第一介质材料层21a具有良好的材料特性和精确的形貌，进而保证依据第一介质材料层21a及其衍生膜层形成的结构的形貌满足预设要求；其中，衍生膜层指的是刻蚀第一介质材料层21a的部分材料形成的膜层。
参考图9，以光刻胶层23(参考图8)为掩膜，刻蚀去除部分所述第一牺牲材料层22(参考图8)，剩余第一牺牲材料层22作为第一牺牲层22a，第一牺牲层22a具有第二凹槽22b；在形成第一牺牲层22a之后，去除光刻胶层23。
本实施例中，利用光刻胶层23作为掩膜，依次刻蚀第一牺牲子层221和第二牺牲子层222，形成暴露第一介质材料层21a的第二凹槽22b，在形成第二凹槽22b之后，去除光刻胶层23，如此，可在同一工艺步骤中刻蚀第一牺牲子层221和第二牺牲子层222，减少刻蚀步骤，降低工艺成本。
在其他实施例中，利用光刻胶层作为掩膜，先刻蚀第二牺牲子层，形成暴露第一牺牲子层顶面的开口图案；在刻蚀部分第二牺牲子层之后，去除光刻胶层；在去除光刻胶层之后，利用剩余的具有开口图案的所述第二牺牲子层作为掩膜，刻蚀第一牺牲子层，形成第二凹槽。如此，有利于光刻胶层的去除工艺对第一介质材料层造成损伤，损伤包括但不限于改变第一介质材料层的形貌特征以及改变第一介质材料层的材料特性。
需要说明的是，刻蚀第一牺牲子层221和第二牺牲子层222的刻蚀剂可以是同一刻蚀剂，也可以是不同刻蚀剂。在一些实施例中，第一介质材料层21a的材料与第二牺牲子层22的材料属于同一类型，通过调整第一介质材料层21a的材料的原子数占比，扩大第一介质材料层21a和第一牺牲子层21之间的材料特性差异，和/或，通过调整第二牺牲子层222的材料的原子数占比，缩小第一牺牲子层221与第二牺牲子层222之间的材料特性差异，最终通过同一刻蚀剂刻蚀第一牺牲子层221和第二牺牲子层222，且刻蚀剂不会对第一介质材料层21a造成损伤。如此，有利于减少刻蚀工艺，降低工艺成本。
参考图10，形成第二介质材料层24a，第二介质材料层24a覆盖第一牺牲层22a的上表面、第二凹槽22b的底部及侧壁，第二凹槽22b侧壁相当于第一牺牲层22a侧壁。
本实施例中，采用原子层沉积工艺形成第二介质材料层24a，以使得第二介质材料层24a的厚度精确满足预设要求，从而使得刻蚀第二介质材料层24a形成的第二介质层具有较高的位置精度，进而使得利用第二介质层作为掩膜刻蚀形成的第一介质层具有较高的位置精度；此外，采用原子层沉积工艺形成第二介质材料层24a，还可以使得第二介质材料层24a具有较高的致密度，即第二介质材料层24a具有较高的结构强度，从而避免第二介质层因结构疏松而发生坍塌。
本实施例中，设置第二介质材料层24a的材料为二氧化硅，二氧化硅材 料的价格较低，有利于降低半导体结构的制作成本；同时，二氧化硅的质地较软，刻蚀二氧化硅材料的速度较快，有利于缩短工艺时长。
参考图11，形成第一介质层21和第二介质层24。
在垂直于衬底20表面的方向上，采用无掩膜干法刻蚀工艺刻蚀第二介质材料层24a(参考图10)，去除位于第一牺牲层22a上表面和第二凹槽22b底部的第二介质材料层24a，以及去除第一牺牲层22a，剩余第二介质材料层24a构成第二介质层24。
利用第二介质层24作为掩膜，刻蚀第一介质材料层21a(参考图10)，去除第二介质层24暴露的第一介质材料层21a，剩余第一介质材料层21a构成第一介质层21，第二介质层24覆盖第一介质层21上表面，第一介质层21和第二介质层24构成绝缘层(未标示)，绝缘层具有第一凹槽24b。
需要说明的是，最终形成的第二介质层24的顶面和侧壁面均为曲面而非平面，最终形成的第二介质层24的顶部宽度小于底部宽度，第二介质层24的底面宽度等于所述第一介质层21的顶面宽度。
参考图12，形成保护层25。
本实施例中，采用沉积工艺形成保护层25，保护层25覆盖第二介质层24的上表面、第一沟槽24b的底部和侧壁，换句话说，保护层25覆盖衬底20、第一介质层21以及第二介质层24暴露的表面。
在一些实施例中，保护层25的材料的硬度大于第二介质层24的材料的硬度，示例性地，保护层25的材料为氮化硅。氮化硅具有硬度高和成本低的特点，由于氮化硅硬度较高，保护层25的厚度可以较薄，无需担心因结构强度不够而发生坍塌的问题，而保护层25的厚度较薄，有利于缩短后续刻蚀去除保护层25的时间，从而缩短刻蚀剂与第一介质层21的接触时间，减轻第一介质层21受到的损伤，以及缩短半导体结构的整体制作时间；此外，保护层25的厚度较薄，有利于缩短保护层25的沉积形成时间，进一步缩短半导体结构的制作时间；此外，保护层25的厚度较薄，以及保护层25的材料价格较低，两者都有利于降低半导体结构的制作成本。
本实施例中，可采用原子层沉积工艺形成保护层25，由于原子层沉积工 艺为逐层沉积，相邻原子或分子之间的间距较小，因此，采用原子层沉积工艺形成的保护层25与第一介质层21和第二介质层24的表面具有较大的接触面积，结合强度较高，在保护层25的材料固化之前，保护层25的材料能够较好地粘附在第一介质层21和第二介质层24表面，保证保护层25的有效形成。
其中，保护层25的材料固化指的是，保护层25的材料在沉积过程中呈现一定的流动性，或者说，保护层25的材料颗粒较小，保护层25的材料在沉积到第一介质层21和第二介质层24的表面之后，需要通过加热或者其他方式进行固化，以保证保护层25具有较高的结构强度。
此外，第二介质层24的至少一个侧面为曲面而非垂直平面，有利于提高保护层25的材料的有效附着率，避免保护层25的材料因附着强度不够而发生坍塌或滑落，保证保护层25的有效形成。
本实施例中，保护层25的厚度为5～10nm，例如7nm、8nm或9nm。保护层25的厚度过厚，沉积时间较长，且浪费原材料；保护层25的厚度过薄，保护层25的结构强度较低，容易发生坍塌，且保护效果较弱，可能在第二介质层24的去除工艺被去除或者被刻穿，进而暴露出第一介质层21的侧壁，导致第一介质层21的侧壁被第二介质层24的刻蚀剂损伤。
参考图13，形成第二牺牲层26。
本实施例中，在去除部分保护层25以暴露第二介质层24之前，形成第二牺牲层26，第二牺牲层26填充满第一沟槽(未标示)且覆盖保护层25暴露的表面，第二牺牲层26的设置，使得后续可通过无掩膜干法刻蚀工艺刻蚀保护层25，以暴露出第二介质层24表面，无需提供额外的掩膜以进行选择性干法刻蚀工艺，有利于降低工艺成本；另外，通过第二牺牲层26的设置，在通过干法刻蚀工艺刻蚀保护层25时，绝缘层(未标示)不容易倾倒，保证了半导体结构的稳定性。其他实施例中，在形成保护层之后，去除部分保护层，以至少暴露第二介质层的部分表面。
在一些实施例中，第二牺牲层26的材料的硬度小于第二介质层24的材料的硬度，示例性地，第二牺牲层26的材料为碳或含碳有机物，第二牺牲层26可通过灰化工艺去除，如此，有利于避免第二牺牲层26的去除工艺对破坏保护层25以及损伤第一介质层21，保证第一介质层21具有良好的结构特性。
需要说明的是，相对于采用无掩膜干法刻蚀工艺刻蚀保护层25，采用平坦化工艺研磨刻蚀保护层25，可能会污染相邻的其他结构。这是因为碳或含碳有机物的质地较软，具备一定的流动性，若采用平坦化工艺研磨刻蚀保护层25，在研磨过程，可能会甩出部分第二牺牲层26的材料，造成溅射污染。
参考图14，去除部分保护层25。
本实施例中，在垂直于衬底20表面的方向上，采用无掩膜干法刻蚀工艺刻蚀第二介质层24、保护层25以及第二牺牲层26，去除部分第二介质层24、部分保护层25以及部分第二牺牲层26，剩余保护层25的上表面与剩余第二介质层24的上表面平齐，即保护层25暴露第二介质层24上表面；由于碳或含碳化合物的质地较为柔软，容易去除，因此，剩余第二牺牲层26的上表面低于剩余保护层25的上表面。
参考图15，去除剩余第二牺牲层26(参考图14)。
本实施例中，在暴露第二介质层24部分表面之后，采用灰化工艺去除剩余第二牺牲层26，此时，第二介质层24起到保护作用和隔离作用，避免灰化工艺对第一介质层21顶面造成损伤，以及避免灰化工艺形成的杂质附着在第一介质层21顶面，保证第一介质层21具有良好特性。
参考16，采用第一湿法刻蚀工艺去除第二介质层24。
本实施例中，第一湿法刻蚀工艺对第二介质层24的材料和第一介质层21的材料的第一刻蚀选择比为5:1～10:1，例如6:1、7:1或8:1；其中，第一湿法刻蚀工艺采用的刻蚀液包括氟化氢铵溶液。其中，氟化氢铵溶液一般为氟化铵和稀释的氟化氢溶液的混合液，该混合液一般用来刻蚀去除二氧化硅溶液。
由于刻蚀选择比与刻蚀过程中的环境温度有关，环境温度越低，刻蚀选择比越高，刻蚀剂对其他膜层的损伤越小，因此，为减轻第一湿法刻蚀工艺对第一介质层21顶面造成的损伤，可在较低的环境温度下进行第一湿法刻蚀工艺，例如150℃以下。
参考图17，采用第二湿法刻蚀工艺去除保护层25(参考16)。
本实施例中，第二湿法刻蚀工艺对保护层25的材料和第一介质层21的材料具有第二刻蚀选择比，为减轻刻蚀工艺对第一介质层21侧壁造成的损伤， 第二刻蚀选择比应当大于第一刻蚀选择比；在一些实施例中，可设置第二刻蚀选择比为第一刻蚀选择比的2～8倍，例如3倍、5倍或7倍，从而保证第一介质层21侧壁表面为相对平滑的表面。
需要说明是的，若设置第二刻蚀选择比与第一刻蚀选择比的比值过高，则可能导致保护层25的刻蚀速率较慢，工艺时间较长；若比值过小，则对第一介质层21侧壁的结构特性的改善较弱，达不到预设的改善效果。
本实施例中，第二湿法刻蚀工艺对保护层25的材料与第一介质层21的材料的刻蚀选择比为20:1～40:1，例如25:1、30:1或35:1；其中，第二湿法刻蚀工艺采用的刻蚀液包括磷酸溶液。磷酸溶液一般作为氮化硅溶液的刻蚀液，可以很好的去除氮化硅薄膜，并且对氧化硅薄膜的损伤很小。
同理如上，由于刻蚀选择比与刻蚀过程中的环境温度有关，环境温度越低，刻蚀选择比越高，刻蚀速率越慢，因此，为减轻第二湿法刻蚀工艺对第一介质层21顶面和侧壁造成的损伤，可在较低的环境温度下进行第二湿法刻蚀工艺，例如150℃以下。
本实施例中，在进行第一湿法刻蚀工艺之前，采用保护层遮盖第一介质层侧壁，避免第一湿法刻蚀工艺对第一介质层侧壁造成损伤；同时，设置第二刻蚀选择比大于第一刻蚀选择比，减轻第二湿法刻蚀工艺对第一介质层表面造成的损伤，使得第一介质层具有良好的结构特性。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种半导体结构的制作方法，包括：
    提供衬底；
    于所述衬底上形成绝缘层，所述绝缘层包括第一介质层和第二介质层；其中，所述绝缘层具有第一沟槽，所述第二介质层覆盖所述第一介质层的上表面；
    形成保护层，所述保护层覆盖所述第二介质层的上表面、所述第一沟槽的底部及侧壁；
    去除部分所述保护层，以暴露所述第二介质层的至少部分表面；
    采用第一湿法刻蚀工艺去除所述第二介质层，所述第一湿法刻蚀工艺对所述第二介质层的材料和所述第一介质层的材料具有第一刻蚀选择比；
    采用第二湿法刻蚀工艺去除所述保护层，所述第二湿法刻蚀工艺对所述保护层的材料和所述第一介质层的材料具有第二刻蚀选择比，所述第二刻蚀选择比大于所述第一刻蚀选择比。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，形成所述第一介质层的材料为氮氧化硅，形成所述第二介质层的材料为二氧化硅，形成所述保护层的材料为氮化硅。
  3. 根据权利要求1所述的半导体结构的制作方法，其中，所述第二刻蚀选择比为所述第一刻蚀选择比的2～8倍。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，所述第一刻蚀选择比为5:1～10:1。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，所述第一湿法刻蚀工艺采用的刻蚀液包括氟化氢铵溶液。
  6. 根据权利要求3所述的半导体结构的制作方法，其中，所述第二刻蚀选择比为20:1～40:1。
  7. 根据权利要求6所述的半导体结构的制作方法，其中，所述第二湿法刻蚀工艺采用的刻蚀液包括磷酸溶液。
  8. 根据权利要求1所述的半导体结构的制作方法，其中，所述于所述衬底上形 成绝缘层的步骤，包括：
    于所述衬底上形成依次堆叠的第一介质材料层和第一牺牲层，所述第一牺牲层具有第二沟槽；
    形成第二介质材料层，所述第二介质材料层覆盖所述第一牺牲层的上表面、所述第二沟槽的底部及侧壁；
    去除位于所述第一牺牲层上表面的所述第二介质材料层，以及去除位于所述第二沟槽底部的所述第二介质材料层，剩余所述第二介质材料层构成所述第二介质层；
    去除所述第一牺牲层，以及去除所述第二介质层暴露的所述第一介质材料层，剩余所述第一介质材料层构成所述第一介质层。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，所述第一牺牲层包含所述第一介质材料层的材料。
  10. 根据权利要求8所述的半导体结构的制作方法，其中，所述第一牺牲层包括第一牺牲子层和第二牺牲子层，所述第一牺牲子层位于所述第二牺牲子层和所述第一介质材料层之间，所述第二牺牲子层的材料与所述第一介质材料层的材料相同。
  11. 根据权利要求8所述的半导体结构的制作方法，其中，形成所述第二介质材料层的工艺为原子层沉积工艺。
  12. 根据权利要求8所述的半导体结构的制作方法，其中，形成所述第一牺牲层的步骤包括：
    于所述第一介质材料层上形成第一牺牲材料层；
    于所述第一牺牲材料层上形成具有图案开口的光刻胶层；
    以所述光刻胶层为掩膜，刻蚀去除部分所述第一牺牲材料层；
    去除所述光刻胶层；
    其中，剩余的所述第一牺牲材料层构成所述第一牺牲层。
  13. 根据权利要求1所述的半导体结构的制作方法，其中，所述去除部分所述保护层的步骤包括：
    利用干法刻蚀工艺刻蚀部分所述保护层和部分所述第二介质层，剩余所述保护层的上表面与剩余所述第二介质层的上表面平齐，所述保护层暴露所述第二介质层的上表面。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，在所述形成保护层的步骤之后，在所述利用干法刻蚀工艺蚀刻部分所述保护层和部分所述第二介质层的步骤之前，还包括：
    形成第二牺牲层，所述第二牺牲层覆盖所述保护层的表面且填充满所述第一沟槽；
    其中，所述干法刻蚀工艺还去除部分所述第二牺牲层，剩余所述第二牺牲层的上表面低于剩余所述保护层的上表面。
  15. 根据权利要求14所述的半导体结构的制作方法，其中，在去除所述第二介质层之前，还包括：
    去除剩余所述第二牺牲层。
  16. 根据权利要求14所述的半导体结构的制作方法，其中，所述保护层的材料的硬度大于所述第二介质层的材料的硬度。
  17. 根据权利要求16所述的半导体结构的制作方法，其中，所述第二牺牲层的材料的硬度小于所述第二介质层的材料的硬度。
  18. 根据权利要求14所述的半导体结构的制作方法，其中，形成所述第二牺牲层的材料为碳。
  19. 根据权利要求18所述的半导体结构的制作方法，其中，采用灰化工艺去除所述第二牺牲层。
  20. 根据权利要求1所述的半导体结构的制作方法，其中，所述第二湿法刻蚀工艺的工艺温度低于150℃。
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