JPS5897855A - モノリシツク集積回路の製造方法 - Google Patents

モノリシツク集積回路の製造方法

Info

Publication number
JPS5897855A
JPS5897855A JP57205593A JP20559382A JPS5897855A JP S5897855 A JPS5897855 A JP S5897855A JP 57205593 A JP57205593 A JP 57205593A JP 20559382 A JP20559382 A JP 20559382A JP S5897855 A JPS5897855 A JP S5897855A
Authority
JP
Japan
Prior art keywords
region
electrode
transistor
oxide layer
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57205593A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0148660B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
ハンス−ユルゲン・ガ−レ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Publication of JPS5897855A publication Critical patent/JPS5897855A/ja
Publication of JPH0148660B2 publication Critical patent/JPH0148660B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP57205593A 1981-11-28 1982-11-25 モノリシツク集積回路の製造方法 Granted JPS5897855A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP81109995.1 1981-11-28
EP81109995A EP0080523B1 (de) 1981-11-28 1981-11-28 Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem Paar von komplementären Feldeffekttransistoren und mindestens einem Bipolartransistor

Publications (2)

Publication Number Publication Date
JPS5897855A true JPS5897855A (ja) 1983-06-10
JPH0148660B2 JPH0148660B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-10-20

Family

ID=8188041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57205593A Granted JPS5897855A (ja) 1981-11-28 1982-11-25 モノリシツク集積回路の製造方法

Country Status (4)

Country Link
US (1) US4475279A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0080523B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5897855A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3175429D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080267A (ja) * 1983-10-07 1985-05-08 Toshiba Corp 半導体集積回路装置の製造方法

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3230077A1 (de) * 1982-08-12 1984-02-16 Siemens AG, 1000 Berlin und 8000 München Integrierte bipolar- und mos-transistoren enthaltende halbleiterschaltung auf einem chip und verfahren zu ihrer herstellung
DE3369030D1 (en) * 1983-04-18 1987-02-12 Itt Ind Gmbh Deutsche Method of making a monolithic integrated circuit comprising at least one insulated gate field-effect transistor
CA1258320A (en) * 1985-04-01 1989-08-08 Madhukar B. Vora Small contactless ram cell
FR2581248B1 (fr) * 1985-04-26 1987-05-29 Efcis Procede de fabrication de transistors a effet de champ et transistors bipolaires lateraux sur un meme substrat
JPS61287159A (ja) * 1985-06-13 1986-12-17 Oki Electric Ind Co Ltd Ｂｉ−ＣＭＯＳ半導体ＩＣ装置の製造方法
EP0219641B1 (de) * 1985-09-13 1991-01-09 Siemens Aktiengesellschaft Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung
US4808548A (en) * 1985-09-18 1989-02-28 Advanced Micro Devices, Inc. Method of making bipolar and MOS devices on same integrated circuit substrate
US4737472A (en) * 1985-12-17 1988-04-12 Siemens Aktiengesellschaft Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate
DE3706278A1 (de) * 1986-02-28 1987-09-03 Canon Kk Halbleitervorrichtung und herstellungsverfahren hierfuer
US4727046A (en) * 1986-07-16 1988-02-23 Fairchild Semiconductor Corporation Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases
US4764482A (en) * 1986-11-21 1988-08-16 General Electric Company Method of fabricating an integrated circuit containing bipolar and MOS transistors
JPS63304657A (ja) * 1987-06-04 1988-12-12 Fujitsu Ltd 半導体装置の製造方法
KR900001062B1 (ko) * 1987-09-15 1990-02-26 강진구 반도체 바이 씨 모오스 장치의 제조방법
US5173760A (en) * 1987-11-03 1992-12-22 Samsung Electronics Co., Ltd. BiCMOS semiconductor device
KR900005353B1 (ko) * 1987-11-03 1990-07-27 삼성전자 주식회사 반도체 장치의 제조방법
JPH01264253A (ja) * 1988-04-15 1989-10-20 Hitachi Ltd 半導体装置の製造方法
KR910009739B1 (ko) * 1988-07-13 1991-11-29 삼성전자 주식회사 반도체장치의 제조방법
US4982257A (en) * 1988-08-01 1991-01-01 International Business Machines Corporation Vertical bipolar transistor with collector and base extensions
US5256582A (en) * 1989-02-10 1993-10-26 Texas Instruments Incorporated Method of forming complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate
US4918026A (en) * 1989-03-17 1990-04-17 Delco Electronics Corporation Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip
US5108938A (en) * 1989-03-21 1992-04-28 Grumman Aerospace Corporation Method of making a trench gate complimentary metal oxide semiconductor transistor
WO1990011616A1 (en) * 1989-03-21 1990-10-04 Grumman Aerospace Corporation Trench gate complimentary metal oxide semiconductor transistor
US5171702A (en) * 1989-07-21 1992-12-15 Texas Instruments Incorporated Method for forming a thick base oxide in a BiCMOS process
EP0606114A1 (en) * 1989-08-11 1994-07-13 Seiko Instruments Inc. Method of producing field effect transistor
US4960726A (en) * 1989-10-19 1990-10-02 International Business Machines Corporation BiCMOS process
US4987089A (en) * 1990-07-23 1991-01-22 Micron Technology, Inc. BiCMOS process and process for forming bipolar transistors on wafers also containing FETs
EP0505877A2 (en) * 1991-03-27 1992-09-30 Seiko Instruments Inc. Impurity doping method with adsorbed diffusion source
DE4319437C1 (de) * 1993-03-05 1994-05-19 Itt Ind Gmbh Deutsche Verfahren zur Herstellung einer monolithisch integrierten Schaltung mit mindestens einem CMOS-Feldeffekttransistor und einem npn-Bipolar-Transistor
US5411900A (en) * 1993-03-05 1995-05-02 Deutsche Itt Industries, Gmbh Method of fabricating a monolithic integrated circuit with at least one CMOS field-effect transistor and one NPN bipolar transistor
JP2776350B2 (ja) * 1995-12-18 1998-07-16 日本電気株式会社 半導体集積回路装置の製造方法
US7772653B1 (en) 2004-02-11 2010-08-10 National Semiconductor Corporation Semiconductor apparatus comprising bipolar transistors and metal oxide semiconductor transistors
US8791546B2 (en) * 2010-10-21 2014-07-29 Freescale Semiconductor, Inc. Bipolar transistors having emitter-base junctions of varying depths and/or doping concentrations

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1362345A (en) * 1973-05-11 1974-08-07 Mullard Ltd Semiconductor device manufacture
US3981072A (en) * 1973-05-25 1976-09-21 Trw Inc. Bipolar transistor construction method
US4066917A (en) * 1976-05-03 1978-01-03 National Semiconductor Corporation Circuit combining bipolar transistor and JFET's to produce a constant voltage characteristic
US4095252A (en) * 1976-12-27 1978-06-13 National Semiconductor Corporation Composite jfet-bipolar transistor structure
US4120707A (en) * 1977-03-30 1978-10-17 Harris Corporation Process of fabricating junction isolated IGFET and bipolar transistor integrated circuit by diffusion
DE2728845A1 (de) * 1977-06-27 1979-01-18 Siemens Ag Verfahren zum herstellen eines hochfrequenztransistors
DE2753704C2 (de) * 1977-12-02 1986-11-06 Bernd Prof. Dr. rer.nat 5841 Holzen Höfflinger Verfahren zum gleichzeitigen Herstellen von mittels Feldoxid isolierten CMOS-Schaltungsanordnungen und Bipolartransistoren
US4225877A (en) * 1978-09-05 1980-09-30 Sprague Electric Company Integrated circuit with C-Mos logic, and a bipolar driver with polysilicon resistors
US4403395A (en) * 1979-02-15 1983-09-13 Texas Instruments Incorporated Monolithic integration of logic, control and high voltage interface circuitry
US4311532A (en) * 1979-07-27 1982-01-19 Harris Corporation Method of making junction isolated bipolar device in unisolated IGFET IC
US4346512A (en) * 1980-05-05 1982-08-31 Raytheon Company Integrated circuit manufacturing method
US4402003A (en) * 1981-01-12 1983-08-30 Supertex, Inc. Composite MOS/bipolar power device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080267A (ja) * 1983-10-07 1985-05-08 Toshiba Corp 半導体集積回路装置の製造方法

Also Published As

Publication number Publication date
DE3175429D1 (en) 1986-11-06
US4475279A (en) 1984-10-09
JPH0148660B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-10-20
EP0080523B1 (de) 1986-10-01
EP0080523A1 (de) 1983-06-08

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