JPS5740955A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5740955A
JPS5740955A JP11627680A JP11627680A JPS5740955A JP S5740955 A JPS5740955 A JP S5740955A JP 11627680 A JP11627680 A JP 11627680A JP 11627680 A JP11627680 A JP 11627680A JP S5740955 A JPS5740955 A JP S5740955A
Authority
JP
Japan
Prior art keywords
layer
film
wiring
gate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11627680A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP11627680A priority Critical patent/JPS5740955A/en
Publication of JPS5740955A publication Critical patent/JPS5740955A/en
Pending legal-status Critical Current

Links

Landscapes

  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the humidity resistance of a semiconductor device having an Si gate MOS field effect transistor, by providing a metal protective film layer and a silicon nitride film protective layer on a semiconductor substrate provided with an insulating layer and an Al wiring layer. CONSTITUTION:A thermal oxide film 2, a gate insulating film 3, a gate conductor section 4 consisting of polycrystalline Si and, source and drain regions 5, 6 are formed on an Si substrete 1. Next, an SiO2 layer 7 including phosphorus is formed at a low temperature by a CVD method to form Al wiring 8. Next, a CVD-SiO2 layer 9 is formed to cover the upper part of the layer 9 with a metal 10 made of Al and the like and an Si3N4 film 11. The layer 9 is protected by the layer 10 and the film 11, so that stable characteristics can be obtained against Na pollution and air pollution.
JP11627680A 1980-08-22 1980-08-22 Semiconductor device Pending JPS5740955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11627680A JPS5740955A (en) 1980-08-22 1980-08-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11627680A JPS5740955A (en) 1980-08-22 1980-08-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5740955A true JPS5740955A (en) 1982-03-06

Family

ID=14683059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11627680A Pending JPS5740955A (en) 1980-08-22 1980-08-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5740955A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6342600U (en) * 1986-09-08 1988-03-22
US5390016A (en) * 1989-12-11 1995-02-14 Canon Kabushiki Kaisha Image forming apparatus and method for prefeeding a sheet to a conveying path from a sheet accommodating device prior to generation of a sheet feeding signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6342600U (en) * 1986-09-08 1988-03-22
US5390016A (en) * 1989-12-11 1995-02-14 Canon Kabushiki Kaisha Image forming apparatus and method for prefeeding a sheet to a conveying path from a sheet accommodating device prior to generation of a sheet feeding signal

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