JPS5762544A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5762544A
JPS5762544A JP55138319A JP13831980A JPS5762544A JP S5762544 A JPS5762544 A JP S5762544A JP 55138319 A JP55138319 A JP 55138319A JP 13831980 A JP13831980 A JP 13831980A JP S5762544 A JPS5762544 A JP S5762544A
Authority
JP
Japan
Prior art keywords
film
fusible pattern
pattern
psg
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55138319A
Other languages
Japanese (ja)
Inventor
Shigenobu Taira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55138319A priority Critical patent/JPS5762544A/en
Publication of JPS5762544A publication Critical patent/JPS5762544A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To prevent the deterioration of the characteristics of a semiconductor device due to the invasion of external contamination by forming fusible pattern on a nitrided silicon film, thereby enhancing the reliability of fusing the fusible pattern. CONSTITUTION:An Si3N4 film 10 is selectively formed on an Si semiconductor substrate 1, the part except the Si3N4 film 10 is selectively oxidized, and a field oxidized film 2 is formed. Then, a fusible pattern 12 is formed on the film 10 with a polycrystalline silicon layer. Then, an insulating film 4, e.g., PSG or the like is formed, windows for respective electrodes are formed, and wiring pattern 6 of aluminum or the like is formed. Thereafter, a protective film 5, e.g., PSG or the like is formed on the overall surface to protect it against external contamination and moisture. A window W is opened to expose the fusible pattern. In this manner, the fusible pattern is formed simultaneously in the step of manufacturing an MOS transistor.
JP55138319A 1980-10-03 1980-10-03 Semiconductor device Pending JPS5762544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55138319A JPS5762544A (en) 1980-10-03 1980-10-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55138319A JPS5762544A (en) 1980-10-03 1980-10-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5762544A true JPS5762544A (en) 1982-04-15

Family

ID=15219112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55138319A Pending JPS5762544A (en) 1980-10-03 1980-10-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5762544A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209030A (en) * 1982-05-28 1983-12-05 セイコーエプソン株式会社 Semiconductor fuse
JPS59956A (en) * 1982-06-25 1984-01-06 Hitachi Ltd Semiconductor device with polysilicon fuse
JPS60210850A (en) * 1984-04-04 1985-10-23 Mitsubishi Electric Corp Manufacture of semiconductor ic device
US5538924A (en) * 1995-09-05 1996-07-23 Vanguard International Semiconductor Co. Method of forming a moisture guard ring for integrated circuit applications

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209030A (en) * 1982-05-28 1983-12-05 セイコーエプソン株式会社 Semiconductor fuse
JPS59956A (en) * 1982-06-25 1984-01-06 Hitachi Ltd Semiconductor device with polysilicon fuse
JPS60210850A (en) * 1984-04-04 1985-10-23 Mitsubishi Electric Corp Manufacture of semiconductor ic device
JPH0520902B2 (en) * 1984-04-04 1993-03-22 Mitsubishi Electric Corp
US5538924A (en) * 1995-09-05 1996-07-23 Vanguard International Semiconductor Co. Method of forming a moisture guard ring for integrated circuit applications

Similar Documents

Publication Publication Date Title
JPS5745967A (en) Semiconductor device
JPS5696850A (en) Semiconductor device and manufacture thereof
JPS5762544A (en) Semiconductor device
JPS56108247A (en) Semiconductor device
EP0124960A3 (en) Semiconductor devices comprising silicides
JPS5748247A (en) Semiconductor integrated circuit device
JPS5681966A (en) Input protecting circuit for semiconductor device
JPS5740967A (en) Integrated circuit device
FR2309979A1 (en) Semiconductor device with switching elements - has connecting points, each with protective coating of silcon dioxide (NL011176)
JPS56100441A (en) Semiconductor ic device with protection element and manufacture thereof
JPS5664460A (en) Semiconductor device
JPS57199224A (en) Semiconductor device
JPS6489457A (en) Manufacture of semiconductor device
KR940012505A (en) Integrated circuit manufacturing method
JPS57210660A (en) Static ram
JPS56133863A (en) Semiconductor device
JPS5740955A (en) Semiconductor device
JPS5635470A (en) Semiconductor device
JPS6482651A (en) Semiconductor integrated circuit device
JPS6489539A (en) Manufacture of semiconductor device
JPS56150864A (en) Semiconductor device
JPS57153473A (en) Semiconductor device with input and output protective circuit and its manufacturing method
JPS5519880A (en) Manufacturing method of semiconductor device
JPS575329A (en) Manufacture of semiconductor device
JPS54889A (en) Semiconductor integrated circuit device and its manufacture