JPS60210850A - Manufacture of semiconductor ic device - Google Patents
Manufacture of semiconductor ic deviceInfo
- Publication number
- JPS60210850A JPS60210850A JP6841684A JP6841684A JPS60210850A JP S60210850 A JPS60210850 A JP S60210850A JP 6841684 A JP6841684 A JP 6841684A JP 6841684 A JP6841684 A JP 6841684A JP S60210850 A JPS60210850 A JP S60210850A
- Authority
- JP
- Japan
- Prior art keywords
- film
- protection film
- poly
- fuse
- laser beam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は大規模集積回路装置(VLSI)の製造方法
に係り、4’HC,同一チップ内に冗長回路を作成して
おいて、VLSIの製造段階において不良回路部が発生
した場合、その部分を上記冗長回路で電気的に接ぎ換え
る方法の改良に関するものである0
〔従来技術〕
上述のようにVLS Iの製造において、不良回路 ′
部が発生しても、冗長回路で置き換える方式は、VLS
Iの製造歩留りの大幅な向上が期待できるもので、この
方式は256キロビツト以上のダイナミックRAM (
Random Access Memory )に主と
して採用されている。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a large-scale integrated circuit device (VLSI). This invention relates to an improvement in the method of electrically replacing a defective circuit section with the above-mentioned redundant circuit when a defective circuit section occurs during the manufacturing process.
Even if a problem occurs, the method of replacing it with a redundant circuit is
This method is expected to significantly improve the manufacturing yield of I, and is suitable for dynamic RAM of 256 kilobits or more (
Random Access Memory).
第1図A″′−Cは従来方法の主要段階での状態を示す
断面図で、まず、第1図Aに示すように、半導体基板(
1)の非活性領域上に酸化膜(2)を介して、切換ヒユ
ーズの役割をする媒体、たとえば、ポリシリコン線(3
)を形成し、その上に表面平坦化、接合特性。。オイ、
。えや。すyカ、x(psoffZ。FIG. 1A''-C is a cross-sectional view showing the main stages of the conventional method. First, as shown in FIG. 1A, the semiconductor substrate (
A medium, such as a polysilicon line (3), which acts as a switching fuse is placed on the non-active area of
), and then surface flattening and bonding properties. . Oi,
. Yeah. Suyka, x (psoffZ.
ンリンガラス(BPSG)からなる保護膜(4)を形成
する。これに対して第1図Bに示すようにネオジム:イ
ットリ、ウム・アルミニウム・ガーネット(Nd:YA
G)レーザ、アルゴン(Ar)イオンレーザなどによっ
て、保護膜(4)に開孔(5)を形成し、その部分にお
いてポリシリコン線(3)を溶断する。次に、第1図C
に示すように、プラズマ窒化膜のようなパッシベーショ
ン膜(6)によって上部を覆って表面を保験し、不純物
や水分の侵入を防止する。A protective film (4) made of glass (BPSG) is formed. On the other hand, as shown in Figure 1B, neodymium:Yttri, aluminum garnet (Nd:YA
G) A hole (5) is formed in the protective film (4) using a laser, an argon (Ar) ion laser, etc., and the polysilicon line (3) is fused at that portion. Next, Figure 1C
As shown in the figure, the upper part is covered with a passivation film (6) such as a plasma nitride film to protect the surface and prevent impurities and moisture from entering.
上側ではレーザ光Iによって保護膜(4)も同時に除去
したが、保護膜(4)にはクラック等のダメージを与え
るに止め、ポリシリコン線(3)を部分的に除去する場
合もある0これはレーザ光重のパワー。On the upper side, the protective film (4) was also removed at the same time by laser beam I, but it only caused damage such as cracks to the protective film (4), and the polysilicon line (3) may be partially removed. is the power of the laser beam.
波長、保毅膜(4)の厚さに依存する0第2図は保護膜
(4)KPSG膜を用いた場合の、PSG膜(4)の膜
厚とそのレーザ光反射係数との関係を示す図で、PSG
膜(4)下のポリシリコン線(3)の光吸収はPSG膜
(4)の膜厚によって大きく変化する。Figure 2 shows the relationship between the thickness of the PSG film (4) and its laser light reflection coefficient when the protective film (4) KPSG film is used. In the diagram shown, PSG
The light absorption of the polysilicon line (3) under the film (4) varies greatly depending on the thickness of the PSG film (4).
従って、PEG膜(4)の膜厚の変化によってポリシリ
コン線(3)の溶断の再現性に問題が生じる。Therefore, a problem arises in the reproducibility of the melting of the polysilicon line (3) due to a change in the thickness of the PEG film (4).
また、上記従来方法の他に、保護膜(4)を堆積する前
に、ポリシリコン線(3)をレーザで溶断する方法も一
部で行われているが、ごの方法ではポリシリコンの飛散
を生じ、この飛散したポリシリコンによって望まない部
分に短絡を生じるという重大な問題点の他に1飛散ポリ
シリコンの付着部分に盛シ上り段差を生じ、その後の工
程への悪影響も心配される。In addition to the conventional method described above, there is also a method in which the polysilicon line (3) is fused with a laser before depositing the protective film (4), but this method prevents polysilicon from scattering. In addition to the serious problem of causing a short circuit in an undesired area due to the scattered polysilicon, there is also concern that it may cause a raised level difference in the area to which the scattered polysilicon is attached, which may have an adverse effect on subsequent processes.
なお、以上溶断のみKついて説明したが、場合によって
は溶断とは反対に、ポリシリコンの両端まで不純物をド
ーピングしておき、中間の高抵抗ポリシリコンにレーザ
光を当ててその領域に不純つな両側から拡散させて電気
的に接続する方法を用いることもある。Note that although we have explained K only for fusing, in some cases, contrary to fusing, it is possible to dope impurities to both ends of the polysilicon, and then shine a laser beam on the high-resistance polysilicon in the middle to inject impurities into that region. A method of electrically connecting by diffusing from both sides may also be used.
第3図は上記従来の方法を用いた場合のVLSI製造工
程を示すフルー図で、「ウェーハエ程工」において、第
1図Aの形態とし、その後K「回路テスト工程IJKよ
って不良部を検出し、「レーザ溶断」によってヒユーズ
の役割をするポリシリコン線(3)を溶断して接ぎ換え
る工程が入る。これは従来のウェーハ製造工程と全く異
なる工程でありクリーンルーム内での管理や、これらの
工程によるウェーハ汚染の回避等に問題が多い。FIG. 3 is a flow diagram showing the VLSI manufacturing process when using the above conventional method. In the "wafer process", the form shown in FIG. Then, there is a step of cutting and replacing the polysilicon wire (3) that functions as a fuse using "laser cutting." This is a completely different process from the conventional wafer manufacturing process, and there are many problems in managing the clean room and avoiding wafer contamination due to these processes.
この発明は以上のような点に鑑みてなされたもので、ヒ
ユーズ媒体にレーザ光を照射して冗長回路との切換を行
なうべき部分ではパッシベーション膜を形成した後に当
該部分のみヒユーズ媒体を直接露出させた上で、レーザ
光を照射するようKすることによって、従来例における
ような保護膜の膜厚の影響を受けることなく、シかも、
レーザ光照射によってヒユーズ媒体が飛散しても回路に
悪影響のないVLS Iの製造方法を提供するものであ
る〇
〔発明の実施例〕
第4図A−Eはこの発明の一実施例の主要工程段階での
状態を示す断面図で、第5図はその工程のフローを示す
図である。This invention was made in view of the above points, and it is possible to form a passivation film in the area where the fuse medium is to be switched with a redundant circuit by irradiating the laser beam with the laser beam, and then directly expose the fuse medium only in that area. Then, by irradiating the laser beam with K, it is possible to protect the film without being affected by the thickness of the protective film as in the conventional example.
This invention provides a method for manufacturing a VLSI that does not have any adverse effect on the circuit even if the fuse medium is scattered by laser beam irradiation. [Embodiment of the Invention] Figures 4A to 4E show the main steps of an embodiment of the invention. FIG. 5 is a sectional view showing the state at each stage, and FIG. 5 is a diagram showing the flow of the process.
まず、第4図Aに示すように第1図Aと同様に、半導体
基板(1)の非活性領域上に酸化M (2) 、ヒユー
ズ媒体としてポリシリコン線(3)、および保mFMと
してのPSG膜(4)を順次形成する。このPEG膜(
4)は通常回路部ではコンタクトと呼ばれる工程でパタ
ーニングとエツチングとが行なわれる。この実施例では
この工程を利用して、第4図BK示すようにPSG膜(
4)のみに開孔(7)を形成する。次に、第4図Cに示
すように開孔(7)の内部を含めてパッシベーション膜
(6)を堆積し、つづいて、第4図DIC示すように上
述の開孔(7)内のパッシベーション膜(6)に開孔(
7)より径の小さい開孔(8)を形成し、その底部にポ
リシリコン線(3)を露出させる。以上の工程は通常の
半導体装置の製造における金属配線後のワイヤボンディ
ングのパッド部の取り出し用開孔の形成工程であり、第
5図のフロー図での「ウェーハエ程」K相当する。これ
でウェーハはほぼその加工工程を終え、「テスト工程」
にまわされる。このテストで回路機能が調べられ、不良
部に対しては「レーザ溶断」の工程で、ヒユーズ媒体で
あるポリシリコン線(3)の溶断を行い、冗長回路との
置換を行う。この実施例では第4図1ijK示すように
、レーザ光重を開孔(8)からポリシリコン線(3)に
照射して溶断部(9)を形成して、この工程段階は完了
する。以下、第5図に示すように、 「溶断部チップ再
テスト」を経て「アセンブリ工程」に移される。First, as shown in FIG. 4A, in the same way as in FIG. PSG films (4) are sequentially formed. This PEG film (
4) In the circuit section, patterning and etching are normally performed in a process called contact. In this example, this process is used to create a PSG film (
An opening (7) is formed only in 4). Next, as shown in FIG. 4C, a passivation film (6) is deposited including the inside of the opening (7), and then, as shown in FIG. A hole is made in the membrane (6) (
7) Form an opening (8) with a smaller diameter and expose the polysilicon line (3) at its bottom. The above process is a process for forming an opening for taking out a pad portion for wire bonding after metal wiring in the manufacturing of a normal semiconductor device, and corresponds to the "wafer etching process" K in the flowchart of FIG. The wafer has now almost completed its processing process and is ready for the "test process".
be passed around. This test examines the circuit function, and for defective parts, the polysilicon wire (3) serving as the fuse medium is blown out in a "laser blowing" process and replaced with a redundant circuit. In this embodiment, as shown in FIG. 4, the process step is completed by irradiating the polysilicon line (3) with a laser beam through the opening (8) to form a fusing portion (9). Thereafter, as shown in Fig. 5, the ``fusion part chip retest'' is carried out, and then the ``assembly process'' is started.
このようにしてポリシリコン線(3)の溶断のためのレ
ーザ光重の照射はポリシリコン線(3)に直接性なわれ
るので、従来方法におけるよりなPEG膜の膜厚の影響
を受けることなく、溶断は再現性よく確実に行なうこと
ができる。更に、この実施例の方法ではレーザ光■の照
射をすべきポリシリコン線(3)の部分を除いて全上面
がパッシベーション膜(6)でりわれだ状態でレーザ光
■の照射を行なうので、溶融によって飛散する物質の耐
着があっても、それはすべてパッシベーション膜(6)
の上であるから全く無害である。In this way, the laser beam irradiation for fusing the polysilicon line (3) is directly applied to the polysilicon line (3), so it is not affected by the thickness of the PEG film as in the conventional method. , fusing can be performed reliably with good reproducibility. Furthermore, in the method of this embodiment, the laser beam (2) is irradiated with the entire upper surface covered with the passivation film (6) except for the portion of the polysilicon line (3) to be irradiated with the laser beam (2). Even if there is resistance to adhesion of substances scattered by melting, it is all due to the passivation film (6)
It is completely harmless because it is above.
以上説明したように、この発明の方法ではVLSIに冗
長回路部を作成しておいて、VLSIの製造段階で不良
部が発生したときに1内部に形成されているヒユーズ媒
体の所要部位忙レーザ光を照射して溶断または導通させ
て上記冗長回路部で上記不良部を置換するに際して、当
該レーザ光を照射すべき部位を除いて全上面にパッシベ
ーションiを形成した後に、レーザ光照射を行なうので
ζヒユーズ媒体は直接露出しておシ、保護膜の膜厚の影
響を受けることなく、レーザ光照射によってヒユーズ媒
体が飛散しても回路に悪影響のない半導体集積回路装置
の製造方法が得られる。As explained above, in the method of the present invention, a redundant circuit section is created in a VLSI, and when a defective section occurs during the manufacturing stage of the VLSI, a laser beam is emitted on the required part of the fuse medium formed inside the VLSI. When replacing the defective part with the redundant circuit section by irradiating it to fuse or conduct, the laser beam irradiation is performed after forming passivation i on the entire upper surface except for the area to be irradiated with the laser beam. Since the fuse medium is directly exposed and is not affected by the thickness of the protective film, it is possible to obtain a method for manufacturing a semiconductor integrated circuit device in which the circuit is not adversely affected even if the fuse medium is scattered by laser beam irradiation.
第1図A−0は従来方法の主要段階での状態を示す断面
図、第2図はヒユーズ媒体上のP8G保設膜の膜厚とレ
ーザ光反射係数との関係を示す図1第3図祉この従来方
法を用いた場合のVL8 Iの製造工程を壓すフロー図
、第4図A−Eはこの発明の一実施例の主要工程段階で
の状態を示す断面図1第5図はその工程のフロー図であ
る。
図において、(1)は半導体基板、(2)は酸化膜、(
3)はヒユーズ媒体(ポリシリコン線) 、(4)は保
護膜(PSG膜)、(G)はパッシベーション膜である
。
なお、図中同一符号は同一または相当部分を示す0
代理人 大岩増雄
第1図 第3図
PSG履導(A)
第4
第5図Figure 1 A-0 is a cross-sectional view showing the state at the main stage of the conventional method, Figure 2 is a diagram showing the relationship between the thickness of the P8G retention film on the fuse medium and the laser beam reflection coefficient. 4. A flow diagram illustrating the manufacturing process of VL8 I using this conventional method. FIG. It is a flow diagram of a process. In the figure, (1) is a semiconductor substrate, (2) is an oxide film, (
3) is a fuse medium (polysilicon line), (4) is a protective film (PSG film), and (G) is a passivation film. In addition, the same reference numerals in the figures indicate the same or equivalent parts.
Claims (2)
、上記半導体集積回路装置内の一部に不良部が生じたと
きに内部に形成されたヒユーズ媒体の所要部位にレーザ
光を照射して溶断まだは導通させて、上記冗長回路部で
上記不良部を置換するに際して、上記ヒユーズ媒体の上
記所要部位を除く上記半導体集積回路装置の全上面にパ
ッシベーション膜を形成した後に上記レーザ光の照射を
行うことを%徴とする半導体集積回路装置の製造方法0(1) A redundant circuit section is formed in the semiconductor integrated circuit device, and when a defective section occurs in a part of the semiconductor integrated circuit device, a laser beam is irradiated to the required part of the fuse medium formed inside the semiconductor integrated circuit device. When replacing the defective part with the redundant circuit section by melting it or making it conductive, a passivation film is formed on the entire upper surface of the semiconductor integrated circuit device except for the required portion of the fuse medium, and then the laser beam is irradiated. A method for manufacturing a semiconductor integrated circuit device that is characterized by performing 0
端部も露呈しないように形成することを特徴とする特許
請求の範囲第1項記載の半導体集積回路装置の製造方法
。(2) The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the passivation film is formed so as not to expose an end of the protective film on the fuse medium.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6841684A JPS60210850A (en) | 1984-04-04 | 1984-04-04 | Manufacture of semiconductor ic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6841684A JPS60210850A (en) | 1984-04-04 | 1984-04-04 | Manufacture of semiconductor ic device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60210850A true JPS60210850A (en) | 1985-10-23 |
JPH0520902B2 JPH0520902B2 (en) | 1993-03-22 |
Family
ID=13373052
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6841684A Granted JPS60210850A (en) | 1984-04-04 | 1984-04-04 | Manufacture of semiconductor ic device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60210850A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6246542A (en) * | 1985-08-26 | 1987-02-28 | Toshiba Corp | Wafer test system |
JPS6471147A (en) * | 1987-08-12 | 1989-03-16 | American Telephone & Telegraph | Solid state circuit with laser-fusible link |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5641898U (en) * | 1979-09-05 | 1981-04-17 | ||
JPS56146268A (en) * | 1980-04-15 | 1981-11-13 | Fujitsu Ltd | Manufacture of semiconductor memory unit |
JPS5762544A (en) * | 1980-10-03 | 1982-04-15 | Fujitsu Ltd | Semiconductor device |
JPS5928374A (en) * | 1982-08-10 | 1984-02-15 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5641898B2 (en) * | 1973-08-17 | 1981-10-01 |
-
1984
- 1984-04-04 JP JP6841684A patent/JPS60210850A/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5641898U (en) * | 1979-09-05 | 1981-04-17 | ||
JPS56146268A (en) * | 1980-04-15 | 1981-11-13 | Fujitsu Ltd | Manufacture of semiconductor memory unit |
JPS5762544A (en) * | 1980-10-03 | 1982-04-15 | Fujitsu Ltd | Semiconductor device |
JPS5928374A (en) * | 1982-08-10 | 1984-02-15 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6246542A (en) * | 1985-08-26 | 1987-02-28 | Toshiba Corp | Wafer test system |
JPS6471147A (en) * | 1987-08-12 | 1989-03-16 | American Telephone & Telegraph | Solid state circuit with laser-fusible link |
Also Published As
Publication number | Publication date |
---|---|
JPH0520902B2 (en) | 1993-03-22 |
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