JPS5587423A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5587423A
JPS5587423A JP16316178A JP16316178A JPS5587423A JP S5587423 A JPS5587423 A JP S5587423A JP 16316178 A JP16316178 A JP 16316178A JP 16316178 A JP16316178 A JP 16316178A JP S5587423 A JPS5587423 A JP S5587423A
Authority
JP
Japan
Prior art keywords
buffer layer
layer
inp
doped
ingaasp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16316178A
Other languages
Japanese (ja)
Inventor
Kenzo Akita
Toshihiro Kusuki
Akio Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16316178A priority Critical patent/JPS5587423A/en
Publication of JPS5587423A publication Critical patent/JPS5587423A/en
Pending legal-status Critical Current

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Landscapes

  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE: To flaten the surface, by employing an InP or InGaAsP epitaxial layer in which Cd is doped as a buffer layer, in the case an epitaxial layer which is to become an active layer is grown on an InP monocrystal substrate, with a buffer layer for lattice alignment being intervened.
CONSTITUTION: A buffer layer 2 made of p-type InP, InGaAsP, or the like, in which Cd is doped, is epitaxially grown at first on a Zn-doped p-type InP mono- crystal 1 in order to improve lattice alignment. Then, an active monocrystal layer 3 having a desired conductive type is epitaxially grown on the buffer layer 2. If InGaAsP is used as the buffer layer 2, lattice misalignment is kept 0.5% or less by selecting a crystal mixing ratio. In this method, flatness and smoothness of the surface are improved, and the characteristics and yield rate of elements manufactured by using said product is greatly enhanced.
COPYRIGHT: (C)1980,JPO&Japio
JP16316178A 1978-12-26 1978-12-26 Semiconductor device Pending JPS5587423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16316178A JPS5587423A (en) 1978-12-26 1978-12-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16316178A JPS5587423A (en) 1978-12-26 1978-12-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5587423A true JPS5587423A (en) 1980-07-02

Family

ID=15768383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16316178A Pending JPS5587423A (en) 1978-12-26 1978-12-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5587423A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02199875A (en) * 1989-01-30 1990-08-08 Nippon Telegr & Teleph Corp <Ntt> Semiconductor element and manufacture thereof
JP2011054787A (en) * 2009-09-02 2011-03-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02199875A (en) * 1989-01-30 1990-08-08 Nippon Telegr & Teleph Corp <Ntt> Semiconductor element and manufacture thereof
JP2011054787A (en) * 2009-09-02 2011-03-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and method for manufacturing semiconductor device

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