JPS54140483A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54140483A
JPS54140483A JP4804278A JP4804278A JPS54140483A JP S54140483 A JPS54140483 A JP S54140483A JP 4804278 A JP4804278 A JP 4804278A JP 4804278 A JP4804278 A JP 4804278A JP S54140483 A JPS54140483 A JP S54140483A
Authority
JP
Japan
Prior art keywords
film
region
sio2
substrate
wiring line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4804278A
Other languages
English (en)
Japanese (ja)
Inventor
Hiroshi Shiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4804278A priority Critical patent/JPS54140483A/ja
Priority to US06/032,427 priority patent/US4306915A/en
Priority to DE19792916364 priority patent/DE2916364A1/de
Publication of JPS54140483A publication Critical patent/JPS54140483A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1404—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
    • H10P32/1406—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/065—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by making at least a portion of the conductive part non-conductive, e.g. by oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/92—Controlling diffusion profile by oxidation

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP4804278A 1978-04-21 1978-04-21 Semiconductor device Pending JPS54140483A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP4804278A JPS54140483A (en) 1978-04-21 1978-04-21 Semiconductor device
US06/032,427 US4306915A (en) 1978-04-21 1979-04-23 Method of making electrode wiring regions and impurity doped regions self-aligned therefrom
DE19792916364 DE2916364A1 (de) 1978-04-21 1979-04-23 Halbleitervorrichtung und verfahren zu ihrer herstellung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4804278A JPS54140483A (en) 1978-04-21 1978-04-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54140483A true JPS54140483A (en) 1979-10-31

Family

ID=12792259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4804278A Pending JPS54140483A (en) 1978-04-21 1978-04-21 Semiconductor device

Country Status (3)

Country Link
US (1) US4306915A (enExample)
JP (1) JPS54140483A (enExample)
DE (1) DE2916364A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63192249A (ja) * 1987-02-05 1988-08-09 Nec Ic Microcomput Syst Ltd 半導体集積回路装置

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1129118A (en) * 1978-07-19 1982-08-03 Tetsushi Sakai Semiconductor devices and method of manufacturing the same
DE2902665A1 (de) * 1979-01-24 1980-08-07 Siemens Ag Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie
DE3023410A1 (de) * 1980-06-23 1982-01-07 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von mos-strukturen
US4335502A (en) * 1980-10-01 1982-06-22 Standard Microsystems Corporation Method for manufacturing metal-oxide silicon devices
US4391650A (en) * 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices
US4382827A (en) * 1981-04-27 1983-05-10 Ncr Corporation Silicon nitride S/D ion implant mask in CMOS device fabrication
JPS57194572A (en) * 1981-05-27 1982-11-30 Clarion Co Ltd Semiconductor device and manufacture thereof
US4445270A (en) * 1982-06-21 1984-05-01 Rca Corporation Low resistance contact for high density integrated circuit
NL8202686A (nl) * 1982-07-05 1984-02-01 Philips Nv Werkwijze ter vervaardiging van een veldeffektinrichting met geisoleerde stuurelektrode, en inrichting vervaardigd volgens de werkwijze.
US4566175A (en) * 1982-08-30 1986-01-28 Texas Instruments Incorporated Method of making insulated gate field effect transistor with a lightly doped drain using oxide sidewall spacer and double implantations
JPS5952849A (ja) * 1982-09-20 1984-03-27 Fujitsu Ltd 半導体装置の製造方法
JPS59108363A (ja) * 1982-12-14 1984-06-22 Olympus Optical Co Ltd 半導体装置の製造方法
US4509991A (en) * 1983-10-06 1985-04-09 International Business Machines Corporation Single mask process for fabricating CMOS structure
GB2190790B (en) * 1986-05-12 1989-12-13 Plessey Co Plc Improvements in transistors
JPH0628266B2 (ja) * 1986-07-09 1994-04-13 株式会社日立製作所 半導体装置の製造方法
US4682404A (en) * 1986-10-23 1987-07-28 Ncr Corporation MOSFET process using implantation through silicon
JPH02502415A (ja) * 1987-12-02 1990-08-02 アドバンスト・マイクロ・ディバイシズ・インコーポレーテッド 半導体素子のための自己整列した、平坦化されたコンタクト
US5081516A (en) * 1987-12-02 1992-01-14 Advanced Micro Devices, Inc. Self-aligned, planarized contacts for semiconductor devices
EP0344277A4 (en) * 1987-12-02 1990-05-14 Advanced Micro Devices Inc SELF-ALIGNED INTERMEDIATE CONNECTIONS FOR SEMICONDUCTOR ARRANGEMENTS.
JPH02502417A (ja) * 1987-12-02 1990-08-02 アドバンスト・マイクロ・ディバイシズ・インコーポレーテッド 半導体素子の製造方法
US5057902A (en) * 1987-12-02 1991-10-15 Advanced Micro Devices, Inc. Self-aligned semiconductor devices
US5198378A (en) * 1988-10-31 1993-03-30 Texas Instruments Incorporated Process of fabricating elevated source/drain transistor
EP0487022B1 (en) * 1990-11-23 1997-04-23 Texas Instruments Incorporated A method of simultaneously fabricating an insulated gate-field-effect transistor and a bipolar transistor
JPH04352436A (ja) * 1991-05-30 1992-12-07 Fujitsu Ltd 半導体装置
US5264384A (en) * 1991-08-30 1993-11-23 Texas Instruments Incorporated Method of making a non-volatile memory cell

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51109782A (en) * 1975-03-20 1976-09-28 Matsushita Electric Industrial Co Ltd Handotaisochino seizohoho
JPS5255475A (en) * 1975-10-31 1977-05-06 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5272582A (en) * 1975-12-15 1977-06-17 Matsushita Electric Ind Co Ltd Production of semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5217720B1 (enExample) * 1971-07-31 1977-05-17
US4127931A (en) * 1974-10-04 1978-12-05 Nippon Electric Co., Ltd. Semiconductor device
US4069067A (en) * 1975-03-20 1978-01-17 Matsushita Electric Industrial Co., Ltd. Method of making a semiconductor device
US4179311A (en) * 1977-01-17 1979-12-18 Mostek Corporation Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides
FR2388410A1 (fr) * 1977-04-20 1978-11-17 Thomson Csf Procede de realisation de transistors a effet de champ de type mos, et transistors realises selon un tel procede
DE2739662A1 (de) * 1977-09-02 1979-03-08 Siemens Ag Verfahren zur herstellung von mos-transistoren

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51109782A (en) * 1975-03-20 1976-09-28 Matsushita Electric Industrial Co Ltd Handotaisochino seizohoho
JPS5255475A (en) * 1975-10-31 1977-05-06 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS5272582A (en) * 1975-12-15 1977-06-17 Matsushita Electric Ind Co Ltd Production of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63192249A (ja) * 1987-02-05 1988-08-09 Nec Ic Microcomput Syst Ltd 半導体集積回路装置

Also Published As

Publication number Publication date
DE2916364C2 (enExample) 1991-02-28
US4306915A (en) 1981-12-22
DE2916364A1 (de) 1979-10-31

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