JPH1168061A - 粗面化導電性膜の形成方法及び半導体装置 - Google Patents

粗面化導電性膜の形成方法及び半導体装置

Info

Publication number
JPH1168061A
JPH1168061A JP9216697A JP21669797A JPH1168061A JP H1168061 A JPH1168061 A JP H1168061A JP 9216697 A JP9216697 A JP 9216697A JP 21669797 A JP21669797 A JP 21669797A JP H1168061 A JPH1168061 A JP H1168061A
Authority
JP
Japan
Prior art keywords
oxide film
storage node
film
conductive film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9216697A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1168061A5 (enExample
Inventor
Yoshihiko Okamoto
佳彦 岡本
Tadashi Yoshida
匡 吉田
Hiroshi Onishi
寛 大西
Kenichi Hanaoka
建一 花岡
Shigeki Nakajima
茂樹 中島
Junichi Tsuchimoto
淳一 土本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Engineering Corp
Mitsubishi Electric Corp
Original Assignee
Renesas Semiconductor Engineering Corp
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Engineering Corp, Mitsubishi Electric Corp filed Critical Renesas Semiconductor Engineering Corp
Priority to JP9216697A priority Critical patent/JPH1168061A/ja
Priority to US09/009,966 priority patent/US5963815A/en
Priority to TW087101876A priority patent/TW411617B/zh
Priority to KR1019980006796A priority patent/KR19990023080A/ko
Priority to DE19809270A priority patent/DE19809270A1/de
Publication of JPH1168061A publication Critical patent/JPH1168061A/ja
Publication of JPH1168061A5 publication Critical patent/JPH1168061A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP9216697A 1997-07-08 1997-08-11 粗面化導電性膜の形成方法及び半導体装置 Pending JPH1168061A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP9216697A JPH1168061A (ja) 1997-08-11 1997-08-11 粗面化導電性膜の形成方法及び半導体装置
US09/009,966 US5963815A (en) 1997-07-08 1998-01-21 Method for forming a surface-roughened conductive film on a semiconductor wafer
TW087101876A TW411617B (en) 1997-08-11 1998-02-11 Forming method for the roughened conductive film and the semiconductor apparatus
KR1019980006796A KR19990023080A (ko) 1997-08-11 1998-03-02 조면화 도전성막의 형성방법및 반도체 장치
DE19809270A DE19809270A1 (de) 1997-08-11 1998-03-04 Bildungsverfahren eines leitenden Filmes mit aufgerauhter Oberfläche und Halbleitereinrichtung mit einem leitenden Film mit aufgerauhter Oberfläche

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9216697A JPH1168061A (ja) 1997-08-11 1997-08-11 粗面化導電性膜の形成方法及び半導体装置

Publications (2)

Publication Number Publication Date
JPH1168061A true JPH1168061A (ja) 1999-03-09
JPH1168061A5 JPH1168061A5 (enExample) 2004-08-12

Family

ID=16692510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9216697A Pending JPH1168061A (ja) 1997-07-08 1997-08-11 粗面化導電性膜の形成方法及び半導体装置

Country Status (5)

Country Link
US (1) US5963815A (enExample)
JP (1) JPH1168061A (enExample)
KR (1) KR19990023080A (enExample)
DE (1) DE19809270A1 (enExample)
TW (1) TW411617B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW408447B (en) * 1999-01-04 2000-10-11 United Microelectronics Corp The formation method of semispherical grained silicon (HSG-Si)
JP2000340644A (ja) * 1999-05-27 2000-12-08 Mitsubishi Electric Corp 半導体装置の製造方法
US20040206998A1 (en) * 2002-08-26 2004-10-21 Renesas Technology Corp. Semiconductor device having a roughened surface electrode and method of manufacturing the same
KR102424963B1 (ko) 2015-07-30 2022-07-25 삼성전자주식회사 집적회로 소자 및 그 제조 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2894361B2 (ja) * 1990-02-16 1999-05-24 三菱電機株式会社 半導体装置およびその製造方法
JPH04290219A (ja) * 1991-03-19 1992-10-14 Nec Corp 多結晶シリコン膜の形成方法
JP3034327B2 (ja) * 1991-03-25 2000-04-17 宮崎沖電気株式会社 キャパシタ電極の形成方法
JP3071284B2 (ja) * 1991-12-20 2000-07-31 宮崎沖電気株式会社 半導体素子の製造方法
JPH05343337A (ja) * 1992-06-10 1993-12-24 Fujitsu Ltd 半導体装置の製造方法
US5811344A (en) * 1997-01-27 1998-09-22 Mosel Vitelic Incorporated Method of forming a capacitor of a dram cell

Also Published As

Publication number Publication date
DE19809270A1 (de) 1999-02-25
US5963815A (en) 1999-10-05
KR19990023080A (ko) 1999-03-25
TW411617B (en) 2000-11-11

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