JPH11501769A - 薄い導電性層に対する改良された半導体コンタクト - Google Patents
薄い導電性層に対する改良された半導体コンタクトInfo
- Publication number
- JPH11501769A JPH11501769A JP8527032A JP52703296A JPH11501769A JP H11501769 A JPH11501769 A JP H11501769A JP 8527032 A JP8527032 A JP 8527032A JP 52703296 A JP52703296 A JP 52703296A JP H11501769 A JPH11501769 A JP H11501769A
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- Prior art keywords
- layer
- opening
- semiconductor device
- region
- contact hole
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000004020 conductor Substances 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 41
- 238000005530 etching Methods 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 239000003990 capacitor Substances 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 claims description 3
- 239000007983 Tris buffer Substances 0.000 claims 2
- 230000005684 electric field Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 143
- 210000004027 cell Anatomy 0.000 description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- 239000013256 coordination polymer Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/312—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with a bit line higher than the capacitor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 導電性層に対して改良されたコンタクトを有する半導体装置であって 、 内部に開口を有する一材料から成る下側層と、 前記下側層上と前記開口内とに形成された導電性材の層と、 前記導電性材層上の上側層であり、それ自体を貫通してエッチングされたコン タクト・ホールを有する上側層と、 前記開口が、前記コンタクト・ホール下方にある前記導電性材層内に局所化さ れた厚い領域を形成するように位置決めされ、寸法付けされ、形作られているこ とと、 前記コンタクト・ホールを介して前記厚い領域に接触している導体と、 を備える半導体装置。 2. 前記導電性材が相似性Cを有しており、 前記導電性材層が、前記開口に隣接した前記下側層の表面に沿った一位置で厚 みT1を有しており、 前記開口が幅Wを有しており、該開口の幅が式: W≦2×T1×Cで決定され ることから成る、請求項1に記載の半導体装置。 3. 前記導電性材が、約0.80の相似性を有するポリシリコンである、請 求項2に記載の半導体装置。 4. 前記上側層のエッチングが前記導電性層に相対する選択性Sを有して 、全体的な実効深さDTEまで延び、前記コンタクト・ホールが名目上の深さDCH を有し、前記導電性材層が厚みTCLを有し、前記開口が深さDを有しており、当 該Dが式: D≧(DTE−DCH)/S−TCLで決定されることから成る、請求項1 に記載の半導体装置。 5. 前記選択性Sが式: S=EO/ECで決定されており、ここでEOが前 記上側層がエッチングされる速度であり、ECが前記導電性層がエッチングされ る速度である、請求項4に記載の半導体装置。 6. 前記上側層のエッチングが選択性Sを有して、全体的な実効深さDTE まで延び、前記コンタクト・ホールが名目上の深さDCHを有し、前記厚い領域が 厚みTTRを有しており、当該TTRが式: TTR≧(DTE−DCH)/Sで決定される 、請求項1に記載の半導体装置。 7. 前記選択性Sが次式: S=EO/ECで決定されており、ここでEOが 前記上側層がエッチングされる速度であり、ECが前記導電性層がエッチングさ れる速度である、請求項6に記載の半導体装置。 8. 下部電極と、該下部電極から誘電体層を介して電気的に分離された上 部電極とを有するキャパシタを更に備え、前記導電性材層が前記上部電極を形成 しており、前記導体がコンタクトを形成しており、該コンタクトを介して基準電 圧が前記上部電極に印加される、請求項1に記載の半導体装置。 9. 半導体装置であって、 半導体基板のメモリセル・アレイ領域内に形成された電界効果トランジスタで あり、前記基板上に形成されたゲート電極と、該ゲート電極の両側における前記 基板の表面内に形成された第1及び第2ソース/ドレイン領域とを具備する電界 効果トランジスタと、 前記メモリセル・アレイ領域内に形成されたキャパシタであり、前記基板上に 形成されて前記第1ソース/ドレイン領域と電気的に接触する下部電極と、前記 下部電極上に形成された誘電体層と、前記下部電極上方における前記誘電体層上 に形成されたポリシリコン上部電極の第1領域とを具備するキャパシタと、 前記メモリセル・アレイ領域に隣接する前記基板の周辺領域内に形成された前 記ポリシリコン上部電極の第2領域と、 前記基板と前記周辺領域内における前記ポリシリコン上部電極の前記第2領域 との間に介在された下側材層であり、内部に開口を有する下側材層と、 前記ポリシリコン上部電極の前記第2領域上に形成された絶縁層であり、それ 自体を貫通するコンタクト・ホールを有する絶縁層と、 前記コンタクト・ホールを介して前記ポリシリコン上部電極の前記第2領域と 接触する導体と、を備え、 前記開口が前記コンタクト・ホール下方に位置決めされていることから成る半 導体装置。 10. 前記コンタクト・ホール下方における前記開口内の前記ポリシリコン上 部電極の前記第2領域内に局所化された厚い領域を更に備える、請求項9に記載 の半導体装置。 11. 導電性層に対して改良されたコンタクトを有する半導体装置を製作す る方法であって、 内部に開口を有する一材料の下側層を形成する段階と、 前記下側層上で且つ前記開口内に導電性材層を形成する段階と、 前記導電性材層上に一材料の上側層を形成して、それを貫通するコンタクト・ ホールをエッチングする段階と、 前記コンタクト・ホール下方における前記開口内の前記導電性材層内に局所化 された厚い領域を形成する段階と、 前記コンタクト・ホールを介して前記厚い領域に接触する導体を形成する段階 と、 の諸段階を含む、半導体装置を製作する方法。 12. 前記導電性材が相似性Cを有し、 前記導電性材層が、前記開口の下方における前記下側層の表面に沿った一位置 で厚みT1を有し、 前記開口が幅Wを有しており、 前記開口の前記幅が式: W≦2×T1×Cで決定される、請求項11に記載の 半導体装置を製作する方法。 13. 前記上側層の前記エッチングが前記導電性層に相対する選択性Sを有 して、全体的な実効深さDTEまで延び、前記コンタクト・ホールが名目上の深さ DCHを有し、前記導電性材層が厚みTCLを有し、前記開口が深さDを有しており 、Dが式: D≧(DTE−DCH)/S−TCLで決定される、請求項11に記載の半 導体を製作する方法。 14. 前記選択性Sが次式: S=EO/ECで決定されており、ここでEOが 前記上側層がエッチングされる速度であり、ECが前記導電性層がエッチングさ れる速度である、請求項13に記載の半導体装置を製作する方法。 15. 前記上側層のエッチングが選択性Sを有して、全体的な実効深さDTE まで延び、前記コンタクト・ホールが名目上の深さDCHを有し、前記厚い領域が 厚みTTRを有しており、当該TTRが式: TTR≧(DTE−DCH)/Sで決定される 、請求項11に記載の半導体装置を製作する方法。 16. 前記選択性Sが次式: S=EO/ECで決定されており、ここでEOが 前記上側層がエッチングされる速度であり、ECが前記導電性層がエッチングさ れる速度である、請求項15に記載の半導体装置を製作する方法。 17. 下部電極と、該下部電極から誘電体層を介して電気的に分離された上 部電極とを有するキャパシタを形成する諸段階を更に含み、前記導電性材層が前 記上部電極を形成しており、前記導体がコンタクトを形成しており、該コンタク トを介して基準電圧が前記上部電極に印加される、請求項11に記載の半導体装 置を作成する方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US39984495A | 1995-03-07 | 1995-03-07 | |
US08/399,844 | 1995-03-07 | ||
PCT/US1996/003074 WO1996027901A1 (en) | 1995-03-07 | 1996-03-05 | Improved semiconductor contacts to thin conductive layers |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11501769A true JPH11501769A (ja) | 1999-02-09 |
JP3903189B2 JP3903189B2 (ja) | 2007-04-11 |
Family
ID=23581195
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52703296A Expired - Lifetime JP3903189B2 (ja) | 1995-03-07 | 1996-03-05 | Dram半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (6) | US5731610A (ja) |
JP (1) | JP3903189B2 (ja) |
KR (1) | KR100271112B1 (ja) |
WO (1) | WO1996027901A1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3903189B2 (ja) * | 1995-03-07 | 2007-04-11 | マイクロン・テクノロジー・インコーポレーテッド | Dram半導体装置 |
US6028002A (en) | 1996-05-15 | 2000-02-22 | Micron Technology, Inc. | Refractory metal roughness reduction using high temperature anneal in hydrides or organo-silane ambients |
US5903058A (en) * | 1996-07-17 | 1999-05-11 | Micron Technology, Inc. | Conductive bumps on die for flip chip application |
US5811350A (en) * | 1996-08-22 | 1998-09-22 | Micron Technology, Inc. | Method of forming contact openings and an electronic component formed from the same and other methods |
TW375805B (en) * | 1997-04-14 | 1999-12-01 | Nanya Technology Co Ltd | Process for preparing contact window in the semiconductor device and its structure |
KR100295636B1 (ko) * | 1997-12-17 | 2001-08-07 | 김영환 | 박막트랜지스터및그제조방법 |
US6747313B1 (en) | 1997-12-17 | 2004-06-08 | Hyundai Electronics Industries Co., Ltd. | Thin film transistor |
US6261948B1 (en) | 1998-07-31 | 2001-07-17 | Micron Technology, Inc. | Method of forming contact openings |
US6249010B1 (en) * | 1998-08-17 | 2001-06-19 | National Semiconductor Corporation | Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture |
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US6391756B1 (en) * | 1999-08-31 | 2002-05-21 | Micron Technology, Inc. | Semiconductor processing methods of forming contact openings |
KR100360592B1 (ko) * | 1999-12-08 | 2002-11-13 | 동부전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US6380576B1 (en) * | 2000-08-31 | 2002-04-30 | Micron Technology, Inc. | Selective polysilicon stud growth |
US7118960B2 (en) * | 2000-08-31 | 2006-10-10 | Micron Technology, Inc. | Selective polysilicon stud growth |
FR2828764B1 (fr) * | 2001-08-16 | 2004-01-23 | St Microelectronics Sa | Circuit integre et son procede de fabrication, et cellule de memoire incorporant un tel circuit |
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-
1996
- 1996-03-05 JP JP52703296A patent/JP3903189B2/ja not_active Expired - Lifetime
- 1996-03-05 KR KR1019970706261A patent/KR100271112B1/ko not_active IP Right Cessation
- 1996-03-05 WO PCT/US1996/003074 patent/WO1996027901A1/en active IP Right Grant
- 1996-10-17 US US08/733,340 patent/US5731610A/en not_active Expired - Lifetime
-
1997
- 1997-02-03 US US08/789,072 patent/US5827770A/en not_active Expired - Lifetime
-
1998
- 1998-01-16 US US09/008,531 patent/US7485587B1/en not_active Expired - Fee Related
-
2005
- 2005-08-26 US US11/213,278 patent/US20050282377A1/en not_active Abandoned
- 2005-08-26 US US11/213,267 patent/US7678691B2/en not_active Expired - Fee Related
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2008
- 2008-12-12 US US12/333,560 patent/US7932174B2/en not_active Expired - Fee Related
Also Published As
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US5827770A (en) | 1998-10-27 |
US20090087987A1 (en) | 2009-04-02 |
KR100271112B1 (ko) | 2000-12-01 |
US20050282376A1 (en) | 2005-12-22 |
KR19980702854A (ko) | 1998-08-05 |
WO1996027901A1 (en) | 1996-09-12 |
US7932174B2 (en) | 2011-04-26 |
US5731610A (en) | 1998-03-24 |
US20050282377A1 (en) | 2005-12-22 |
US7678691B2 (en) | 2010-03-16 |
US7485587B1 (en) | 2009-02-03 |
JP3903189B2 (ja) | 2007-04-11 |
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