JPH1145949A5 - - Google Patents
Info
- Publication number
- JPH1145949A5 JPH1145949A5 JP1997201363A JP20136397A JPH1145949A5 JP H1145949 A5 JPH1145949 A5 JP H1145949A5 JP 1997201363 A JP1997201363 A JP 1997201363A JP 20136397 A JP20136397 A JP 20136397A JP H1145949 A5 JPH1145949 A5 JP H1145949A5
- Authority
- JP
- Japan
- Prior art keywords
- impurity diffusion
- transistor
- region
- layer
- diffusion region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9201363A JPH1145949A (ja) | 1997-07-28 | 1997-07-28 | スタティック型半導体記憶装置およびその製造方法 |
| US09/010,473 US5886388A (en) | 1997-07-28 | 1998-01-21 | Static semiconductor memory device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9201363A JPH1145949A (ja) | 1997-07-28 | 1997-07-28 | スタティック型半導体記憶装置およびその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1145949A JPH1145949A (ja) | 1999-02-16 |
| JPH1145949A5 true JPH1145949A5 (https=) | 2005-05-19 |
Family
ID=16439822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9201363A Pending JPH1145949A (ja) | 1997-07-28 | 1997-07-28 | スタティック型半導体記憶装置およびその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5886388A (https=) |
| JP (1) | JPH1145949A (https=) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239491B1 (en) | 1998-05-18 | 2001-05-29 | Lsi Logic Corporation | Integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level, and process for making same |
| JP4565700B2 (ja) * | 1999-05-12 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2001077213A (ja) * | 1999-09-08 | 2001-03-23 | Mitsubishi Electric Corp | スタティック型半導体記憶装置および半導体装置 |
| JP3645137B2 (ja) * | 1999-10-18 | 2005-05-11 | Necエレクトロニクス株式会社 | 半導体記憶装置 |
| JP4471504B2 (ja) * | 2001-01-16 | 2010-06-02 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US6589823B1 (en) | 2001-02-22 | 2003-07-08 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug |
| JP2002373946A (ja) * | 2001-06-13 | 2002-12-26 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
| FR2843481B1 (fr) | 2002-08-08 | 2005-09-16 | Soisic | Memoire sur substrat du type silicium sur isolant |
| KR100450683B1 (ko) * | 2002-09-04 | 2004-10-01 | 삼성전자주식회사 | Soi 기판에 형성되는 에스램 디바이스 |
| US6762464B2 (en) * | 2002-09-17 | 2004-07-13 | Intel Corporation | N-p butting connections on SOI substrates |
| JP3684232B2 (ja) * | 2003-04-25 | 2005-08-17 | 株式会社東芝 | 半導体装置 |
| US20040222422A1 (en) * | 2003-05-08 | 2004-11-11 | Wein-Town Sun | CMOS inverter layout |
| JP2006049784A (ja) * | 2003-08-28 | 2006-02-16 | Renesas Technology Corp | 半導体記憶装置及びその製造方法 |
| WO2005096381A1 (en) * | 2004-04-01 | 2005-10-13 | Soisic | Improved layout of a sram memory cell |
| JP2008016480A (ja) * | 2006-07-03 | 2008-01-24 | Sony Corp | 半導体記憶装置及びその製造方法 |
| CN102725841B (zh) * | 2010-01-15 | 2016-10-05 | 株式会社半导体能源研究所 | 半导体器件 |
| JP5588298B2 (ja) * | 2010-10-14 | 2014-09-10 | 株式会社東芝 | 半導体装置 |
| CN116057713A (zh) * | 2020-08-06 | 2023-05-02 | 索尼半导体解决方案公司 | 半导体装置和电子设备 |
| CN114792727A (zh) * | 2021-01-25 | 2022-07-26 | 台湾积体电路制造股份有限公司 | 半导体器件及其使用方法 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6281055A (ja) * | 1985-10-04 | 1987-04-14 | Sony Corp | 半導体記憶装置 |
| GB8700347D0 (en) * | 1987-01-08 | 1987-02-11 | Inmos Ltd | Memory cell |
| US5194749A (en) * | 1987-11-30 | 1993-03-16 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| JP3070099B2 (ja) * | 1990-12-13 | 2000-07-24 | ソニー株式会社 | スタティックram |
| JPH04359562A (ja) * | 1991-06-06 | 1992-12-11 | Casio Comput Co Ltd | 薄膜トランジスタおよびその製造方法 |
| US5206533A (en) * | 1991-06-24 | 1993-04-27 | Texas Instruments Incorporated | Transistor device with resistive coupling |
| JPH05174580A (ja) * | 1991-12-24 | 1993-07-13 | Sony Corp | スタティックランダムアクセスメモリ |
-
1997
- 1997-07-28 JP JP9201363A patent/JPH1145949A/ja active Pending
-
1998
- 1998-01-21 US US09/010,473 patent/US5886388A/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100344488B1 (ko) | 반도체집적회로장치 | |
| JPH1145949A5 (https=) | ||
| US5955768A (en) | Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell | |
| EP0596824B1 (en) | Semiconductor device and wafer structure having a planar buried interconnect prepared by wafer bonding | |
| US7804132B2 (en) | Semiconductor device | |
| US5886388A (en) | Static semiconductor memory device and manufacturing method thereof | |
| KR100333021B1 (ko) | 반도체 장치 및 그 제조방법 | |
| JPH104179A (ja) | 半導体装置 | |
| US20080179676A1 (en) | Semiconductor memory device | |
| JP4471504B2 (ja) | 半導体記憶装置 | |
| US7265423B2 (en) | Technique for fabricating logic elements using multiple gate layers | |
| JP2004103851A (ja) | スタティック型半導体記憶装置 | |
| KR20020062590A (ko) | 반도체메모리장치 및 그 제조방법 | |
| JP2023036057A (ja) | スタンダードセル構造 | |
| JP3266644B2 (ja) | ゲートアレイ装置 | |
| JP2000124450A (ja) | 半導体装置 | |
| JP7843432B2 (ja) | スタンダードセル構造 | |
| US6124638A (en) | Semiconductor device and a method of manufacturing the same | |
| JP3942192B2 (ja) | 半導体集積回路装置およびその製造方法 | |
| JP3981798B2 (ja) | 半導体記憶装置及びその製造方法 | |
| JP2008041895A (ja) | 半導体装置およびその製造方法 | |
| JP4417445B2 (ja) | 半導体装置及びその製造方法 | |
| JP3447871B2 (ja) | 配線の形成方法及び半導体素子の形成方法 | |
| JP2751893B2 (ja) | 半導体記憶装置およびその製造方法 | |
| JPWO1997005652A1 (ja) | Sram装置およびその製造方法 |