JPH11353880A5 - - Google Patents

Info

Publication number
JPH11353880A5
JPH11353880A5 JP1999125702A JP12570299A JPH11353880A5 JP H11353880 A5 JPH11353880 A5 JP H11353880A5 JP 1999125702 A JP1999125702 A JP 1999125702A JP 12570299 A JP12570299 A JP 12570299A JP H11353880 A5 JPH11353880 A5 JP H11353880A5
Authority
JP
Japan
Prior art keywords
reference voltage
ground line
virtual ground
coupled
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP1999125702A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11353880A (ja
Filing date
Publication date
Priority claimed from US09/073,670 external-priority patent/US5986923A/en
Application filed filed Critical
Publication of JPH11353880A publication Critical patent/JPH11353880A/ja
Publication of JPH11353880A5 publication Critical patent/JPH11353880A5/ja
Withdrawn legal-status Critical Current

Links

JP11125702A 1998-05-06 1999-05-06 高密度記憶装置に適用するｓｒａｍセルの非対象デザイン Withdrawn JPH11353880A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US073670 1998-05-06
US09/073,670 US5986923A (en) 1998-05-06 1998-05-06 Method and apparatus for improving read/write stability of a single-port SRAM cell

Publications (2)

Publication Number Publication Date
JPH11353880A JPH11353880A (ja) 1999-12-24
JPH11353880A5 true JPH11353880A5 (enExample) 2006-06-22

Family

ID=22115071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11125702A Withdrawn JPH11353880A (ja) 1998-05-06 1999-05-06 高密度記憶装置に適用するｓｒａｍセルの非対象デザイン

Country Status (2)

Country Link
US (1) US5986923A (enExample)
JP (1) JPH11353880A (enExample)

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US6104631A (en) * 1997-12-17 2000-08-15 National Scientific Corp. Static memory cell with load circuit using a tunnel diode
US6016390A (en) * 1998-01-29 2000-01-18 Artisan Components, Inc. Method and apparatus for eliminating bitline voltage offsets in memory devices
US6295232B2 (en) * 1999-12-08 2001-09-25 International Business Machines Corporation Dual-to-single-rail converter for the read out of static storage arrays
US6507527B1 (en) * 2000-08-07 2003-01-14 Advanced Micro Devices, Inc. Memory line discharge before sensing
US6304482B1 (en) * 2000-11-21 2001-10-16 Silicon Integrated Systems Corp. Apparatus of reducing power consumption of single-ended SRAM
US6560139B2 (en) * 2001-03-05 2003-05-06 Intel Corporation Low leakage current SRAM array
US6618289B2 (en) * 2001-10-29 2003-09-09 Atmel Corporation High voltage bit/column latch for Vcc operation
JP3983032B2 (ja) * 2001-11-09 2007-09-26 沖電気工業株式会社 半導体記憶装置
JP3520283B2 (ja) * 2002-04-16 2004-04-19 沖電気工業株式会社 半導体記憶装置
EP1398793B1 (fr) * 2002-09-06 2014-05-21 CSEM Centre Suisse d'Electronique et de Microtechnique S.A. - Recherche et Développement Circuit intégré numérique réalisé en technologie MOS
US20040090820A1 (en) * 2002-11-08 2004-05-13 Saroj Pathak Low standby power SRAM
JP4388274B2 (ja) * 2002-12-24 2009-12-24 株式会社ルネサステクノロジ 半導体記憶装置
JP4370100B2 (ja) 2003-01-10 2009-11-25 パナソニック株式会社 半導体記憶装置
JP4167127B2 (ja) 2003-05-29 2008-10-15 沖電気工業株式会社 半導体集積装置
JP2004362695A (ja) * 2003-06-05 2004-12-24 Renesas Technology Corp 半導体記憶装置
US7532536B2 (en) * 2003-10-27 2009-05-12 Nec Corporation Semiconductor memory device
US7403640B2 (en) * 2003-10-27 2008-07-22 Hewlett-Packard Development Company, L.P. System and method for employing an object-oriented motion detector to capture images
US7023744B1 (en) * 2003-11-18 2006-04-04 Xilinx, Inc. Reconfigurable SRAM-ROM cell
US7126861B2 (en) * 2003-12-30 2006-10-24 Intel Corporation Programmable control of leakage current
US6972987B1 (en) * 2004-05-27 2005-12-06 Altera Corporation Techniques for reducing power consumption in memory cells
KR100604876B1 (ko) * 2004-07-02 2006-07-31 삼성전자주식회사 다양한 ｐｖｔ 변화에 대해서도 안정적인 버츄얼 레일스킴을 적용한 ｓｒａｍ 장치
WO2006083034A1 (ja) * 2005-02-03 2006-08-10 Nec Corporation 半導体記憶装置及びその駆動方法
JP4912016B2 (ja) * 2005-05-23 2012-04-04 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7242600B2 (en) * 2005-10-28 2007-07-10 Qualcomm Incorporated Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground
JP2007193928A (ja) * 2005-12-19 2007-08-02 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR100665853B1 (ko) 2005-12-26 2007-01-09 삼성전자주식회사 고집적 스태이틱 랜덤 억세스 메모리에 채용하기 적합한적층 메모리 셀
TWI433149B (zh) 2006-04-28 2014-04-01 Mosaid Technologies Inc 降低ｓｒａｍ漏電流之電路
US7471588B2 (en) * 2006-05-05 2008-12-30 Altera Corporation Dual port random-access-memory circuitry
US20080212392A1 (en) * 2007-03-02 2008-09-04 Infineon Technologies Multiple port mugfet sram
US7755926B2 (en) * 2007-06-13 2010-07-13 International Business Machines Corporation 3-D SRAM array to improve stability and performance
US20080310220A1 (en) * 2007-06-13 2008-12-18 International Business Machines Corporation 3-d sram array to improve stability and performance
US7545670B2 (en) * 2007-07-10 2009-06-09 Sony Computer Entertainment Inc. Dual word line or floating bit line low power SRAM
US7796418B2 (en) * 2008-03-19 2010-09-14 Broadcom Corporation Programmable memory cell
US8319548B2 (en) * 2009-02-18 2012-11-27 Freescale Semiconductor, Inc. Integrated circuit having low power mode voltage regulator
US20100283445A1 (en) * 2009-02-18 2010-11-11 Freescale Semiconductor, Inc. Integrated circuit having low power mode voltage regulator
JP5317900B2 (ja) 2009-09-14 2013-10-16 ルネサスエレクトロニクス株式会社 半導体集積回路およびその動作方法
TWI419162B (zh) * 2009-11-03 2013-12-11 Univ Hsiuping Sci & Tech 具放電路徑之單埠靜態隨機存取記憶體
TWI425509B (zh) * 2009-11-17 2014-02-01 Univ Hsiuping Sci & Tech 具放電路徑之雙埠靜態隨機存取記憶體
TWI426514B (zh) * 2009-11-17 2014-02-11 Univ Hsiuping Sci & Tech 寫入操作時降低電源電壓之單埠靜態隨機存取記憶體
TWI426515B (zh) * 2009-11-17 2014-02-11 Univ Hsiuping Sci & Tech 寫入操作時降低電源電壓之單埠ｓｒａｍ
TWI425510B (zh) * 2010-02-04 2014-02-01 Univ Hsiuping Sci & Tech 具低待機電流之單埠靜態隨機存取記憶體
US8400819B2 (en) * 2010-02-26 2013-03-19 Freescale Semiconductor, Inc. Integrated circuit having variable memory array power supply voltage
US9875788B2 (en) * 2010-03-25 2018-01-23 Qualcomm Incorporated Low-power 5T SRAM with improved stability and reduced bitcell size
US20120057399A1 (en) * 2010-09-07 2012-03-08 Shyh-Jye Jou Asymmetric virtual-ground single-ended sram and system thereof
TWI478164B (zh) * 2011-03-11 2015-03-21 Hsiuping Inst Technology 具待機啟動電路之雙埠靜態隨機存取記憶體
US9035629B2 (en) 2011-04-29 2015-05-19 Freescale Semiconductor, Inc. Voltage regulator with different inverting gain stages
TWI478165B (zh) * 2012-04-27 2015-03-21 Univ Hsiuping Sci & Tech 具高效能之單埠靜態隨機存取記憶體
KR20150048427A (ko) * 2013-10-28 2015-05-07 에스케이하이닉스 주식회사 디스차지 회로
JP6392082B2 (ja) * 2014-10-31 2018-09-19 ルネサスエレクトロニクス株式会社 半導体記憶装置
US9293192B1 (en) 2014-12-02 2016-03-22 International Business Machines Corporation SRAM cell with dynamic split ground and split wordline
TWI573138B (zh) * 2015-05-08 2017-03-01 修平學校財團法人修平科技大學 ７ｔ雙埠靜態隨機存取記憶體（七）
TWI573139B (zh) * 2015-10-07 2017-03-01 修平學校財團法人修平科技大學 單埠靜態隨機存取記憶體
TWI579846B (zh) * 2015-12-10 2017-04-21 修平學校財團法人修平科技大學 ７ｔ雙埠靜態隨機存取記憶體
CN105719689A (zh) * 2016-03-31 2016-06-29 西安紫光国芯半导体有限公司 一种增强存储单元写能力的静态随机存储器及其写操作方法
CN105976859B (zh) * 2016-05-20 2019-05-17 西安紫光国芯半导体有限公司 一种超低写功耗的静态随机存储器写操作的控制方法
KR102827204B1 (ko) * 2020-10-27 2025-07-01 삼성전자주식회사 정적 램 메모리 장치 및 이의 동작 방법

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Publication number Priority date Publication date Assignee Title
JPH0746506B2 (ja) * 1985-09-30 1995-05-17 株式会社東芝 半導体メモリ装置
US5831896A (en) * 1996-12-17 1998-11-03 International Business Machines Corporation Memory cell
US5764564A (en) * 1997-03-11 1998-06-09 Xilinx, Inc. Write-assisted memory cell and method of operating same
US5808933A (en) * 1997-03-28 1998-09-15 International Business Machines Corporation Zero-write-cycle memory cell apparatus

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