JPH11121932A - 多層配線板及び多層プリント配線板 - Google Patents

多層配線板及び多層プリント配線板

Info

Publication number
JPH11121932A
JPH11121932A JP9303694A JP30369497A JPH11121932A JP H11121932 A JPH11121932 A JP H11121932A JP 9303694 A JP9303694 A JP 9303694A JP 30369497 A JP30369497 A JP 30369497A JP H11121932 A JPH11121932 A JP H11121932A
Authority
JP
Japan
Prior art keywords
layer
wiring board
printed wiring
conductor circuit
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9303694A
Other languages
English (en)
Japanese (ja)
Inventor
Yoji Mori
要二 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP9303694A priority Critical patent/JPH11121932A/ja
Priority to EP98944278A priority patent/EP1030365A4/en
Priority to CN 200610094490 priority patent/CN1909226B/zh
Priority to CN 200610100699 priority patent/CN101013685B/zh
Priority to US09/529,597 priority patent/US6392898B1/en
Priority to PCT/JP1998/004350 priority patent/WO1999021224A1/ja
Priority to CN 200610101861 priority patent/CN1901180A/zh
Priority to CNB988102153A priority patent/CN1161838C/zh
Priority to KR1020007004062A priority patent/KR100691296B1/ko
Priority to EP07122506A priority patent/EP1895589A3/en
Priority to CN200610101902XA priority patent/CN1971899B/zh
Priority to CNB2004100456190A priority patent/CN100426491C/zh
Priority to EP07122502A priority patent/EP1895586A3/en
Priority to CN 200710085293 priority patent/CN100547780C/zh
Priority to EP07122509A priority patent/EP1895587A3/en
Priority to CNB2006101018385A priority patent/CN100431144C/zh
Priority to US10/850,584 priority patent/USRE41242E1/en
Priority to TW087117123A priority patent/TW398162B/zh
Priority to MYPI98004731A priority patent/MY128327A/en
Publication of JPH11121932A publication Critical patent/JPH11121932A/ja
Priority to US09/905,974 priority patent/US6411519B2/en
Priority to US09/906,078 priority patent/US6487088B2/en
Priority to US09/905,973 priority patent/US6490170B2/en
Priority to US09/906,076 priority patent/US20010054513A1/en
Priority to US10/876,287 priority patent/USRE41051E1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP9303694A 1997-10-17 1997-10-17 多層配線板及び多層プリント配線板 Pending JPH11121932A (ja)

Priority Applications (24)

Application Number Priority Date Filing Date Title
JP9303694A JPH11121932A (ja) 1997-10-17 1997-10-17 多層配線板及び多層プリント配線板
CNB2004100456190A CN100426491C (zh) 1997-10-17 1998-09-28 封装基板
EP07122509A EP1895587A3 (en) 1997-10-17 1998-09-28 Semiconductor package substrate
CN 200710085293 CN100547780C (zh) 1997-10-17 1998-09-28 封装基板
US09/529,597 US6392898B1 (en) 1997-10-17 1998-09-28 Package substrate
CN 200610094490 CN1909226B (zh) 1997-10-17 1998-09-28 封装基板
CN 200610101861 CN1901180A (zh) 1997-10-17 1998-09-28 封装基板
CNB988102153A CN1161838C (zh) 1997-10-17 1998-09-28 封装基板
CNB2006101018385A CN100431144C (zh) 1997-10-17 1998-09-28 封装基板
EP07122506A EP1895589A3 (en) 1997-10-17 1998-09-28 Semiconductor package substrate
CN200610101902XA CN1971899B (zh) 1997-10-17 1998-09-28 封装基板
EP98944278A EP1030365A4 (en) 1997-10-17 1998-09-28 SUBSTRATE OF A HOUSING
EP07122502A EP1895586A3 (en) 1997-10-17 1998-09-28 Semiconductor package substrate
CN 200610100699 CN101013685B (zh) 1997-10-17 1998-09-28 封装基板
PCT/JP1998/004350 WO1999021224A1 (fr) 1997-10-17 1998-09-28 Substrat d'un boitier
KR1020007004062A KR100691296B1 (ko) 1997-10-17 1998-09-28 패키지기판
US10/850,584 USRE41242E1 (en) 1997-10-17 1998-09-28 Package substrate
TW087117123A TW398162B (en) 1997-10-17 1998-10-15 Package substrate board
MYPI98004731A MY128327A (en) 1997-10-17 1998-10-16 Package board
US09/905,974 US6411519B2 (en) 1997-10-17 2001-07-17 Package substrate
US09/906,078 US6487088B2 (en) 1997-10-17 2001-07-17 Package substrate
US09/905,973 US6490170B2 (en) 1997-10-17 2001-07-17 Package substrate
US09/906,076 US20010054513A1 (en) 1997-10-17 2001-07-17 Package substrate
US10/876,287 USRE41051E1 (en) 1997-10-17 2004-06-25 Package substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9303694A JPH11121932A (ja) 1997-10-17 1997-10-17 多層配線板及び多層プリント配線板

Publications (1)

Publication Number Publication Date
JPH11121932A true JPH11121932A (ja) 1999-04-30

Family

ID=17924125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9303694A Pending JPH11121932A (ja) 1997-10-17 1997-10-17 多層配線板及び多層プリント配線板

Country Status (2)

Country Link
JP (1) JPH11121932A (zh)
CN (5) CN1909226B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005135453A (ja) * 2003-10-28 2005-05-26 Elpida Memory Inc メモリシステム及びメモリモジュール
CN111629536A (zh) * 2020-05-22 2020-09-04 东莞联桥电子有限公司 一种偶数多层电路板的压合制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI463925B (zh) * 2011-07-08 2014-12-01 Unimicron Technology Corp 封裝基板及其製法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866507A (en) * 1986-05-19 1989-09-12 International Business Machines Corporation Module for packaging semiconductor integrated circuit chips on a base substrate
US4963697A (en) * 1988-02-12 1990-10-16 Texas Instruments Incorporated Advanced polymers on metal printed wiring board
JPH07273243A (ja) * 1994-03-30 1995-10-20 Toshiba Corp 半導体パッケージ
JPH08236654A (ja) * 1995-02-23 1996-09-13 Matsushita Electric Ind Co Ltd チップキャリアとその製造方法
JP2763020B2 (ja) * 1995-04-27 1998-06-11 日本電気株式会社 半導体パッケージ及び半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005135453A (ja) * 2003-10-28 2005-05-26 Elpida Memory Inc メモリシステム及びメモリモジュール
CN111629536A (zh) * 2020-05-22 2020-09-04 东莞联桥电子有限公司 一种偶数多层电路板的压合制作方法
CN111629536B (zh) * 2020-05-22 2023-10-27 东莞联桥电子有限公司 一种偶数多层电路板的压合制作方法

Also Published As

Publication number Publication date
CN1909226B (zh) 2012-09-26
CN100431144C (zh) 2008-11-05
CN1897264A (zh) 2007-01-17
CN1901180A (zh) 2007-01-24
CN1909226A (zh) 2007-02-07
CN101017806A (zh) 2007-08-15
CN101013685A (zh) 2007-08-08
CN100547780C (zh) 2009-10-07
CN101013685B (zh) 2012-05-09

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Effective date: 20050901

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