JPH10116243A - メモリ装置 - Google Patents
メモリ装置Info
- Publication number
- JPH10116243A JPH10116243A JP9107173A JP10717397A JPH10116243A JP H10116243 A JPH10116243 A JP H10116243A JP 9107173 A JP9107173 A JP 9107173A JP 10717397 A JP10717397 A JP 10717397A JP H10116243 A JPH10116243 A JP H10116243A
- Authority
- JP
- Japan
- Prior art keywords
- address
- data
- coupled
- signal
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims abstract description 59
- 230000004044 response Effects 0.000 claims description 10
- 239000000872 buffer Substances 0.000 description 24
- 238000010586 diagram Methods 0.000 description 9
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 238000004883 computer application Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
Landscapes
- Dram (AREA)
- Memory System (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/641,659 US5640361A (en) | 1996-05-01 | 1996-05-01 | Memory architecture |
| US641,659 | 1996-05-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10116243A true JPH10116243A (ja) | 1998-05-06 |
| JPH10116243A5 JPH10116243A5 (https=) | 2005-03-17 |
Family
ID=24573328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9107173A Pending JPH10116243A (ja) | 1996-05-01 | 1997-04-24 | メモリ装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5640361A (https=) |
| JP (1) | JPH10116243A (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970051229A (ko) * | 1995-12-22 | 1997-07-29 | 김광호 | 비동기 발생신호를 사용하는 반도체 메모리 장치 |
| KR100329734B1 (ko) * | 1998-04-03 | 2002-06-20 | 박종섭 | 어드레스입력및데이터입력용으로동일단자를겸용하는반도체메모리장치 |
| JP4439033B2 (ja) * | 1999-04-16 | 2010-03-24 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| JP5439567B1 (ja) * | 2012-10-11 | 2014-03-12 | 株式会社東芝 | 半導体装置 |
| US9972610B2 (en) * | 2015-07-24 | 2018-05-15 | Intel Corporation | System-in-package logic and method to control an external packaged memory device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4479178A (en) * | 1981-07-02 | 1984-10-23 | Texas Instruments Incorporated | Quadruply time-multiplex information bus |
| US5444665A (en) * | 1985-06-17 | 1995-08-22 | Hitachi, Ltd. | Semiconductor memory device |
| JPS62250593A (ja) * | 1986-04-23 | 1987-10-31 | Hitachi Ltd | ダイナミツク型ram |
| JPS6355797A (ja) * | 1986-08-27 | 1988-03-10 | Fujitsu Ltd | メモリ |
| JP2648840B2 (ja) * | 1988-11-22 | 1997-09-03 | 株式会社日立製作所 | 半導体記憶装置 |
| JP3024767B2 (ja) * | 1989-08-29 | 2000-03-21 | 株式会社日立製作所 | アドレス供給システム |
| US5530955A (en) * | 1991-04-01 | 1996-06-25 | Matsushita Electric Industrial Co., Ltd. | Page memory device capable of short cycle access of different pages by a plurality of data processors |
| TW212243B (https=) * | 1991-11-15 | 1993-09-01 | Hitachi Seisakusyo Kk | |
| US5402384A (en) * | 1992-04-24 | 1995-03-28 | Citizen Watch Co., Ltd. | Dynamic ram |
| JPH0831573B2 (ja) * | 1992-10-01 | 1996-03-27 | 日本電気株式会社 | ダイナミックram |
-
1996
- 1996-05-01 US US08/641,659 patent/US5640361A/en not_active Expired - Lifetime
-
1997
- 1997-04-24 JP JP9107173A patent/JPH10116243A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US5640361A (en) | 1997-06-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040426 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040426 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20051214 |
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| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20051220 |
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| A02 | Decision of refusal |
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