JPH10116243A5 - - Google Patents

Info

Publication number
JPH10116243A5
JPH10116243A5 JP1997107173A JP10717397A JPH10116243A5 JP H10116243 A5 JPH10116243 A5 JP H10116243A5 JP 1997107173 A JP1997107173 A JP 1997107173A JP 10717397 A JP10717397 A JP 10717397A JP H10116243 A5 JPH10116243 A5 JP H10116243A5
Authority
JP
Japan
Prior art keywords
coupled
address
data signals
electrical contacts
receive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1997107173A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10116243A (ja
Filing date
Publication date
Priority claimed from US08/641,659 external-priority patent/US5640361A/en
Application filed filed Critical
Publication of JPH10116243A publication Critical patent/JPH10116243A/ja
Publication of JPH10116243A5 publication Critical patent/JPH10116243A5/ja
Pending legal-status Critical Current

Links

JP9107173A 1996-05-01 1997-04-24 メモリ装置 Pending JPH10116243A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/641,659 US5640361A (en) 1996-05-01 1996-05-01 Memory architecture
US641,659 1996-05-01

Publications (2)

Publication Number Publication Date
JPH10116243A JPH10116243A (ja) 1998-05-06
JPH10116243A5 true JPH10116243A5 (https=) 2005-03-17

Family

ID=24573328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9107173A Pending JPH10116243A (ja) 1996-05-01 1997-04-24 メモリ装置

Country Status (2)

Country Link
US (1) US5640361A (https=)
JP (1) JPH10116243A (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970051229A (ko) * 1995-12-22 1997-07-29 김광호 비동기 발생신호를 사용하는 반도체 메모리 장치
KR100329734B1 (ko) * 1998-04-03 2002-06-20 박종섭 어드레스입력및데이터입력용으로동일단자를겸용하는반도체메모리장치
JP4439033B2 (ja) * 1999-04-16 2010-03-24 株式会社ルネサステクノロジ 半導体記憶装置
JP5439567B1 (ja) * 2012-10-11 2014-03-12 株式会社東芝 半導体装置
US9972610B2 (en) * 2015-07-24 2018-05-15 Intel Corporation System-in-package logic and method to control an external packaged memory device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4479178A (en) * 1981-07-02 1984-10-23 Texas Instruments Incorporated Quadruply time-multiplex information bus
US5444665A (en) * 1985-06-17 1995-08-22 Hitachi, Ltd. Semiconductor memory device
JPS62250593A (ja) * 1986-04-23 1987-10-31 Hitachi Ltd ダイナミツク型ｒａｍ
JPS6355797A (ja) * 1986-08-27 1988-03-10 Fujitsu Ltd メモリ
JP2648840B2 (ja) * 1988-11-22 1997-09-03 株式会社日立製作所 半導体記憶装置
JP3024767B2 (ja) * 1989-08-29 2000-03-21 株式会社日立製作所 アドレス供給システム
US5530955A (en) * 1991-04-01 1996-06-25 Matsushita Electric Industrial Co., Ltd. Page memory device capable of short cycle access of different pages by a plurality of data processors
TW212243B (https=) * 1991-11-15 1993-09-01 Hitachi Seisakusyo Kk
US5402384A (en) * 1992-04-24 1995-03-28 Citizen Watch Co., Ltd. Dynamic ram
JPH0831573B2 (ja) * 1992-10-01 1996-03-27 日本電気株式会社 ダイナミックｒａｍ

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