KR920001528A - 동기형 데이터전송회로를 갖춘 다이나믹형 반도체기억장치 - Google Patents
동기형 데이터전송회로를 갖춘 다이나믹형 반도체기억장치 Download PDFInfo
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- KR920001528A KR920001528A KR1019910009199A KR910009199A KR920001528A KR 920001528 A KR920001528 A KR 920001528A KR 1019910009199 A KR1019910009199 A KR 1019910009199A KR 910009199 A KR910009199 A KR 910009199A KR 920001528 A KR920001528 A KR 920001528A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 DRAM에 사용되는 데이터전송회로를 도시한 블럭다이어그램,
제2도는 제1도에 도시한 데이터전송회로의 동작을 설명하기 위한 타이밍차트,
제3도는 본 발명의 제1실시예에 다른 DRAM을 도시한 블럭다이어그램.
Claims (4)
- 서로 교차하는 복수개의 비트선과 복수개의 워드선 및, 상기 각 비트선과 워드선의 교차위치에 배치된 다이나믹형 메모리셀을 갖춘 메모리셀어레이(27)와; 이 메모리셀어레이(27)중 선택된 메모리셀과 데이터의 송수신을 행하는 센스앰프(28); 출력단자를 갖추고 있으면서 외부로부터 공급된 행어드레스와 열어드레스를 저장하도록된 어드레스버퍼(21,22); 상기 메모리셀어레이(27)의 부근에 위치하고 있으면서 상기 어드레스버퍼(21,22)로부터 출력된 열어드레스에 따라 비트선의 선택을 행하는 열디코더(25); 상기 메모리셀어레이(27)의 부근에 위치하고 있으면서 상기 어드레스버퍼(21,22)로부터 출력된 행어드레스에 따라 워드선의 선택을 행하는 행디코더(26); 상기 열디코더(25)에 의해 선택적으로 제어되는 전송게이트를 매개하여 상기 비트선에 접속되는 제1데이터선(29); 이 제1데이터선(29)에 접속된 데이터입출력버퍼(30); 이 데이터입출력버퍼(30)를 매개하여 상기 제1데이터선(29)에 접속된 제2데이터선(31); 상기 어드레스버퍼(22)의 출력단자에 연결되어 있으면서 상기 어드레스버퍼(22)로부터 출력된 행 및 열어드레스신호의 천이를 검출하여 그 검출신호를 출력하도록 된 어드레스 천이검출회로(33); 상기 제2데이터선(31)에 접속되어 있으면서 정상동작중에는 상기 제2데이터선(31)을 리세트상태로 유지시키는 한편, 상기 어드레스천이검출회로(33)로부터의 출력신호에 대응하여 상기 제2데이터선(31)을 일시적으로 리세트상태로부터 해제시키도록 된 이퀄라이즈회로(35)및; 상기 제2데이터선(31)에 접속되어 있으면서 상기 어드레스천이검출회로(33)로부터의 출력신호에 대응하여 상기 제2데이터선(31)으로 전송된 데이터를 래치시키도록 된 데이터래치회로(32)를 구비하여 구성된 것을 특징으로 하는 동기형 데이터전송회로를 갖춘 다이나믹형 반도체기억장치.
- 제1항에 있어서, 상기 데이터입출력버퍼(30)가 커런트미러형의 CMOS차동증폭기로 구성된 것을 특징으로 하는 동기형 데이터전송회로를 갖춘 다이나믹형 반도체기억장치.
- 제1항에 있어서, 상기 데이터래치회로(32)가 CMOS플립플롭으로 구성된 것을 특징으로 하는 동기형 데이터 전송회로를 갖춘 다이나믹형 반도체기억장치.
- 제1항에 있어서, 상기 제2데이터선(31)은 적어도 2개의 데이터선(311,312)으로 분할되고, 이 분할된 2개의 데이터선(311,312)중 데이터선(311)에 입력단이 접속됨과 더불어 데이터선(312)에 출력단이 접속된 적어도 1개의 중간버퍼(34)와, 상기 2개의 데이터선(311,312)에 접속되어 있으면서 각 데이터선(311,312)의 이퀄라이즈상태를 독립적으로 해제시키도록 된 적어도 2개의 이퀄라이즈회로(351,352)를 구비하여 구성된 것을 특징으로 하는 동기형 데이터전송회로를 갖춘 다이나믹형 반도체기억장치.※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2-144442 | 1990-06-04 | ||
JP2144442A JPH0438793A (ja) | 1990-06-04 | 1990-06-04 | データ転送制御回路およびこれを用いたダイナミック型半導体記憶装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR920001528A true KR920001528A (ko) | 1992-01-30 |
Family
ID=15362316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910009199A KR920001528A (ko) | 1990-06-04 | 1991-06-04 | 동기형 데이터전송회로를 갖춘 다이나믹형 반도체기억장치 |
Country Status (4)
Country | Link |
---|---|
US (2) | US6108254A (ko) |
JP (1) | JPH0438793A (ko) |
KR (1) | KR920001528A (ko) |
DE (1) | DE4118301C2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100299468B1 (ko) * | 1997-10-20 | 2001-09-06 | 아끼구사 나오유끼 | 전력절약화동기회로및그것을갖는반도체기억장치 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2830594B2 (ja) * | 1992-03-26 | 1998-12-02 | 日本電気株式会社 | 半導体メモリ装置 |
KR0146530B1 (ko) * | 1995-05-25 | 1998-09-15 | 김광호 | 단속제어회로를 구비한 반도체 메모리 장치와 제어방법 |
JPH10255480A (ja) * | 1997-03-14 | 1998-09-25 | Oki Electric Ind Co Ltd | センスアンプ |
JP3206737B2 (ja) * | 1998-03-27 | 2001-09-10 | 日本電気株式会社 | ラッチ回路 |
US6282138B1 (en) * | 1999-02-25 | 2001-08-28 | Micron Technology, Inc. | Latched sense amplifier with tri-state outputs |
KR100322541B1 (ko) * | 1999-07-14 | 2002-03-18 | 윤종용 | 입출력 라인쌍 등화회로 및 이를 구비한 메모리 장치 |
JP4216415B2 (ja) * | 1999-08-31 | 2009-01-28 | 株式会社ルネサステクノロジ | 半導体装置 |
DE10034255C2 (de) * | 2000-07-14 | 2002-05-16 | Infineon Technologies Ag | Schaltungsanordnung zum Lesen und Schreiben von Information an einem Speicherzellenfeld |
DE10044837C1 (de) * | 2000-09-11 | 2001-09-13 | Infineon Technologies Ag | Schaltungsanordnung und Verfahren zum Detektieren eines unerwünschten Angriffs auf eine integrierte Schaltung |
KR100380271B1 (ko) * | 2000-12-27 | 2003-04-18 | 주식회사 하이닉스반도체 | 메인 앰프의 출력 드라이버 회로 |
KR100412131B1 (ko) | 2001-05-25 | 2003-12-31 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 셀 데이타 보호회로 |
JP2005243158A (ja) * | 2004-02-27 | 2005-09-08 | Elpida Memory Inc | ダイナミック型半導体記憶装置 |
US7227799B2 (en) * | 2005-04-29 | 2007-06-05 | Infineon Technologies Ag | Sense amplifier for eliminating leakage current due to bit line shorts |
JP4191217B2 (ja) * | 2006-09-20 | 2008-12-03 | エルピーダメモリ株式会社 | 半導体装置 |
KR100824779B1 (ko) * | 2007-01-11 | 2008-04-24 | 삼성전자주식회사 | 반도체 메모리 장치의 데이터 출력 경로 및 데이터 출력방법 |
FR2935059B1 (fr) * | 2008-08-12 | 2012-05-11 | Groupe Des Ecoles De Telecommunications Get Ecole Nationale Superieure Des Telecommunications Enst | Procede de detection d'anomalies dans un circuit de cryptographie protege par logique differentielle et circuit mettant en oeuvre un tel procede |
JP5262706B2 (ja) * | 2008-12-26 | 2013-08-14 | 富士通セミコンダクター株式会社 | 半導体集積回路,データ転送システムおよびデータ転送方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5968889A (ja) * | 1982-10-08 | 1984-04-18 | Toshiba Corp | 半導体記憶装置 |
JPS60119698A (ja) * | 1983-12-01 | 1985-06-27 | Fujitsu Ltd | 半導体メモリ |
JPH0787037B2 (ja) * | 1984-03-02 | 1995-09-20 | 沖電気工業株式会社 | 半導体メモリ回路のデータ書込方法 |
JPS62226498A (ja) * | 1986-03-28 | 1987-10-05 | Hitachi Ltd | 半導体記憶装置 |
JPS637591A (ja) * | 1986-06-25 | 1988-01-13 | Nec Corp | アドレスマルチプレクス型半導体メモリ |
JPS6376193A (ja) * | 1986-09-19 | 1988-04-06 | Fujitsu Ltd | 半導体記憶装置 |
JPH0612632B2 (ja) * | 1987-02-27 | 1994-02-16 | 日本電気株式会社 | メモリ回路 |
JP2569538B2 (ja) * | 1987-03-17 | 1997-01-08 | ソニー株式会社 | メモリ装置 |
US4891792A (en) * | 1987-09-04 | 1990-01-02 | Hitachi, Ltd. | Static type semiconductor memory with multi-stage sense amplifier |
US5146247A (en) * | 1987-12-26 | 1992-09-08 | Canon Kabushiki Kaisha | Information retrieval apparatus |
US4922461A (en) * | 1988-03-30 | 1990-05-01 | Kabushiki Kaisha Toshiba | Static random access memory with address transition detector |
US5146427A (en) * | 1989-08-30 | 1992-09-08 | Hitachi Ltd. | High speed semiconductor memory having a direct-bypass signal path |
-
1990
- 1990-06-04 JP JP2144442A patent/JPH0438793A/ja active Pending
-
1991
- 1991-06-04 KR KR1019910009199A patent/KR920001528A/ko not_active Application Discontinuation
- 1991-06-04 DE DE4118301A patent/DE4118301C2/de not_active Expired - Lifetime
-
1993
- 1993-11-12 US US08/150,782 patent/US6108254A/en not_active Expired - Fee Related
-
2000
- 2000-08-10 US US09/636,504 patent/US6337821B1/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100299468B1 (ko) * | 1997-10-20 | 2001-09-06 | 아끼구사 나오유끼 | 전력절약화동기회로및그것을갖는반도체기억장치 |
Also Published As
Publication number | Publication date |
---|---|
JPH0438793A (ja) | 1992-02-07 |
US6337821B1 (en) | 2002-01-08 |
US6108254A (en) | 2000-08-22 |
DE4118301A1 (de) | 1991-12-05 |
DE4118301C2 (de) | 1996-02-01 |
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