JPH09237857A5 - - Google Patents

Info

Publication number
JPH09237857A5
JPH09237857A5 JP1997045857A JP4585797A JPH09237857A5 JP H09237857 A5 JPH09237857 A5 JP H09237857A5 JP 1997045857 A JP1997045857 A JP 1997045857A JP 4585797 A JP4585797 A JP 4585797A JP H09237857 A5 JPH09237857 A5 JP H09237857A5
Authority
JP
Japan
Prior art keywords
layer
substrate
back surface
via opening
adhesion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997045857A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09237857A (ja
JP4117042B2 (ja
Filing date
Publication date
Application filed filed Critical
Publication of JPH09237857A publication Critical patent/JPH09237857A/ja
Publication of JPH09237857A5 publication Critical patent/JPH09237857A5/ja
Application granted granted Critical
Publication of JP4117042B2 publication Critical patent/JP4117042B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP04585797A 1996-02-28 1997-02-28 半導体装置 Expired - Fee Related JP4117042B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9602492 1996-02-28
FR9602492 1996-02-28

Publications (3)

Publication Number Publication Date
JPH09237857A JPH09237857A (ja) 1997-09-09
JPH09237857A5 true JPH09237857A5 (enrdf_load_html_response) 2005-02-03
JP4117042B2 JP4117042B2 (ja) 2008-07-09

Family

ID=9489670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04585797A Expired - Fee Related JP4117042B2 (ja) 1996-02-28 1997-02-28 半導体装置

Country Status (4)

Country Link
US (1) US5844321A (enrdf_load_html_response)
EP (1) EP0793269B1 (enrdf_load_html_response)
JP (1) JP4117042B2 (enrdf_load_html_response)
DE (1) DE69712562T2 (enrdf_load_html_response)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3724110B2 (ja) 1997-04-24 2005-12-07 三菱電機株式会社 半導体装置の製造方法
US20080099537A1 (en) * 2006-10-31 2008-05-01 Raytheon Company Method for sealing vias in a substrate
DE102009028037A1 (de) * 2009-07-27 2011-02-03 Robert Bosch Gmbh Bauelement mit einer elektrischen Durchkontaktierung, Verfahren zur Herstellung eines Bauelementes und Bauelementsystem
US9576873B2 (en) * 2011-12-14 2017-02-21 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with routable trace and method of manufacture thereof
JP7168280B2 (ja) * 2018-06-26 2022-11-09 住友電工デバイス・イノベーション株式会社 半導体装置、および、半導体チップの搭載方法
US10861792B2 (en) 2019-03-25 2020-12-08 Raytheon Company Patterned wafer solder diffusion barrier

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02162735A (ja) * 1988-12-15 1990-06-22 Fujitsu Ltd 半導体装置及びその製造方法
US5027189A (en) * 1990-01-10 1991-06-25 Hughes Aircraft Company Integrated circuit solder die-attach design and method
FR2665574B1 (fr) * 1990-08-03 1997-05-30 Thomson Composants Microondes Procede d'interconnexion entre un circuit integre et un circuit support, et circuit integre adapte a ce procede.
US5350662A (en) * 1992-03-26 1994-09-27 Hughes Aircraft Company Maskless process for forming refractory metal layer in via holes of GaAs chips
US5635762A (en) * 1993-05-18 1997-06-03 U.S. Philips Corporation Flip chip semiconductor device with dual purpose metallized ground conductor
JP3350152B2 (ja) 1993-06-24 2002-11-25 三菱電機株式会社 半導体装置およびその製造方法

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