JPH09186289A - 多層積層化集積回路チップ組立体 - Google Patents

多層積層化集積回路チップ組立体

Info

Publication number
JPH09186289A
JPH09186289A JP8328260A JP32826096A JPH09186289A JP H09186289 A JPH09186289 A JP H09186289A JP 8328260 A JP8328260 A JP 8328260A JP 32826096 A JP32826096 A JP 32826096A JP H09186289 A JPH09186289 A JP H09186289A
Authority
JP
Japan
Prior art keywords
chip
wiring
wiring pad
assembly
top surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8328260A
Other languages
English (en)
Japanese (ja)
Inventor
Yinon Degani
デガニ イノン
Thomas Dixon Dudderar
ディキソン ダッデラー トーマス
Joon Han Byung
ジョーン ハン ビュン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of JPH09186289A publication Critical patent/JPH09186289A/ja
Pending legal-status Critical Current

Links

Classifications

    • H10W72/071
    • H10W90/00
    • H10W90/20
    • H10W90/291
    • H10W90/722
    • H10W90/724
    • H10W90/732
    • H10W90/752
    • H10W90/754

Landscapes

  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
JP8328260A 1995-12-28 1996-12-09 多層積層化集積回路チップ組立体 Pending JPH09186289A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58022095A 1995-12-28 1995-12-28
US580220 1995-12-28

Publications (1)

Publication Number Publication Date
JPH09186289A true JPH09186289A (ja) 1997-07-15

Family

ID=24320199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8328260A Pending JPH09186289A (ja) 1995-12-28 1996-12-09 多層積層化集積回路チップ組立体

Country Status (4)

Country Link
EP (1) EP0782191A2 (enExample)
JP (1) JPH09186289A (enExample)
KR (1) KR970053214A (enExample)
TW (1) TW315515B (enExample)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181002B1 (en) * 1998-12-22 2001-01-30 Sharp Kabushiki Kaisha Semiconductor device having a plurality of semiconductor chips
KR100537835B1 (ko) * 2000-10-19 2005-12-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조방법
US7071574B1 (en) 2000-01-17 2006-07-04 Renesas Technology Corp. Semiconductor device and its wiring method
CN100369248C (zh) * 2004-02-13 2008-02-13 株式会社东芝 叠层mcp及其制造方法
JP2008159607A (ja) 2006-12-20 2008-07-10 Fujitsu Ltd 半導体装置及びその製造方法
CN100411172C (zh) * 2004-03-01 2008-08-13 株式会社日立制作所 半导体器件
US7453153B2 (en) 2005-03-29 2008-11-18 Sanyo Electric Co., Ltd. Circuit device
CN100461401C (zh) * 2004-03-24 2009-02-11 三垦电气株式会社 半导体器件
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0890989A4 (en) 1997-01-24 2006-11-02 Rohm Co Ltd SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
DE19743264C2 (de) * 1997-09-30 2002-01-17 Infineon Technologies Ag Verfahren zur Herstellung einer Emulationsschaltkreisanordnung sowie Emulationsschaltkreisanordnung mit zwei integrierten Schaltkreisen
US6413797B2 (en) 1997-10-09 2002-07-02 Rohm Co., Ltd. Semiconductor device and method for making the same
CA2218307C (en) * 1997-10-10 2006-01-03 Gennum Corporation Three dimensional packaging configuration for multi-chip module assembly
JP2000164796A (ja) * 1998-11-27 2000-06-16 Nec Corp マルチチップモジュール
JP3662461B2 (ja) 1999-02-17 2005-06-22 シャープ株式会社 半導体装置、およびその製造方法
JP2001044358A (ja) * 1999-07-28 2001-02-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6605875B2 (en) * 1999-12-30 2003-08-12 Intel Corporation Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size
US6344401B1 (en) * 2000-03-09 2002-02-05 Atmel Corporation Method of forming a stacked-die integrated circuit chip package on a water level
KR100464561B1 (ko) * 2000-04-11 2004-12-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
JP2002176137A (ja) 2000-09-28 2002-06-21 Toshiba Corp 積層型半導体デバイス
EP1332654B1 (en) 2000-11-10 2005-01-12 Unitive Electronics, Inc. Methods of positioning components using liquid prime movers and related structures
US6863209B2 (en) 2000-12-15 2005-03-08 Unitivie International Limited Low temperature methods of bonding components
JP3558595B2 (ja) * 2000-12-22 2004-08-25 松下電器産業株式会社 半導体チップ,半導体チップ群及びマルチチップモジュール
US6762122B2 (en) 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
EP1367646A1 (fr) * 2002-05-23 2003-12-03 Valtronic S.A. Module électronique
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
AU2003256360A1 (en) 2002-06-25 2004-01-06 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US7531898B2 (en) 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
TWI225899B (en) 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
US7427557B2 (en) 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
TW200603698A (en) 2004-04-13 2006-01-16 Unitive International Ltd Methods of forming solder bumps on exposed metal pads and related structures
US7700409B2 (en) 2004-05-24 2010-04-20 Honeywell International Inc. Method and system for stacking integrated circuits
US7863720B2 (en) 2004-05-24 2011-01-04 Honeywell International Inc. Method and system for stacking integrated circuits
FR2873853B1 (fr) * 2004-07-27 2006-12-15 St Microelectronics Sa Dispositif electronique comprenant plusieurs plaquettes de circuits empilees et procede de realisation d'un tel dispositif
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7932615B2 (en) 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
KR102012505B1 (ko) 2012-12-20 2019-08-20 에스케이하이닉스 주식회사 토큰 링 루프를 갖는 스택 패키지
TWI799312B (zh) * 2022-07-05 2023-04-11 瑞昱半導體股份有限公司 輸出入埠電路及其晶片

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181002B1 (en) * 1998-12-22 2001-01-30 Sharp Kabushiki Kaisha Semiconductor device having a plurality of semiconductor chips
US7071574B1 (en) 2000-01-17 2006-07-04 Renesas Technology Corp. Semiconductor device and its wiring method
US7288837B2 (en) 2000-01-17 2007-10-30 Renesas Technology Corp. Semiconductor device and its writing method
US7547963B2 (en) 2000-01-17 2009-06-16 Renesas Technology Corp. Semiconductor device and its wiring method
KR100537835B1 (ko) * 2000-10-19 2005-12-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조방법
CN100369248C (zh) * 2004-02-13 2008-02-13 株式会社东芝 叠层mcp及其制造方法
CN100411172C (zh) * 2004-03-01 2008-08-13 株式会社日立制作所 半导体器件
CN100461401C (zh) * 2004-03-24 2009-02-11 三垦电气株式会社 半导体器件
US7453153B2 (en) 2005-03-29 2008-11-18 Sanyo Electric Co., Ltd. Circuit device
JP2008159607A (ja) 2006-12-20 2008-07-10 Fujitsu Ltd 半導体装置及びその製造方法
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package
US9633973B2 (en) 2012-12-20 2017-04-25 Samsung Electronics Co., Ltd. Semiconductor package

Also Published As

Publication number Publication date
TW315515B (enExample) 1997-09-11
KR970053214A (ko) 1997-07-29
EP0782191A2 (en) 1997-07-02

Similar Documents

Publication Publication Date Title
JPH09186289A (ja) 多層積層化集積回路チップ組立体
US7468551B2 (en) Multiple chips bonded to packaging structure with low noise and multiple selectable functions
KR100311356B1 (ko) 집적회로패키지
TWI479630B (zh) 具中心接觸件之增強堆疊微電子總成以及其之系統、模組及配置
CN100438024C (zh) 半导体封装及层叠型半导体封装
KR101013562B1 (ko) 큐브 반도체 패키지
JPS6352776B2 (enExample)
KR20010060208A (ko) 적층형 반도체 디바이스
JP2003110084A (ja) 半導体装置
JP2003133518A (ja) 半導体モジュール
JP2001024150A (ja) 半導体装置
CN101740530A (zh) 集成电路基底
US20050116322A1 (en) Circuit module
KR100573302B1 (ko) 와이어 본딩을 이용한 패키지 스택 및 그 제조 방법
KR100731235B1 (ko) 반도체 장치
JP2003332377A (ja) フリップチップボンディングのための有機基板
US6563208B2 (en) Semiconductor package with conductor impedance selected during assembly
US6586825B1 (en) Dual chip in package with a wire bonded die mounted to a substrate
JP2005057271A (ja) 同一平面上に横配置された機能部及び実装部を具備する半導体チップパッケージ及びその積層モジュール
JP2001177049A (ja) 半導体装置及びicカード
JP2008535229A (ja) 接続ボールが設けられた電子パッケージの積重ねを含む薄厚電子モジュール
KR101169688B1 (ko) 반도체 장치 및 적층 반도체 패키지
CN120413553A (zh) 一种叠层存储芯片连接系统、方法及设备
CN117393534A (zh) 一种芯片封装结构及电子设备
KR20110016028A (ko) 적층 반도체 패키지