JPH08227992A - Pmosfet半導体デバイス - Google Patents
Pmosfet半導体デバイスInfo
- Publication number
- JPH08227992A JPH08227992A JP7335700A JP33570095A JPH08227992A JP H08227992 A JPH08227992 A JP H08227992A JP 7335700 A JP7335700 A JP 7335700A JP 33570095 A JP33570095 A JP 33570095A JP H08227992 A JPH08227992 A JP H08227992A
- Authority
- JP
- Japan
- Prior art keywords
- channel region
- substrate
- pmosfet
- polycrystalline silicon
- indium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01031—Gallium [Ga]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US34798094A | 1994-12-01 | 1994-12-01 | |
| US347980 | 1994-12-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08227992A true JPH08227992A (ja) | 1996-09-03 |
Family
ID=23366146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7335700A Pending JPH08227992A (ja) | 1994-12-01 | 1995-12-01 | Pmosfet半導体デバイス |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US5710055A (enExample) |
| JP (1) | JPH08227992A (enExample) |
| KR (1) | KR960026938A (enExample) |
| CN (1) | CN1132941A (enExample) |
| DE (1) | DE19544945A1 (enExample) |
| TW (1) | TW304301B (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012028534A (ja) * | 2010-07-22 | 2012-02-09 | Fujitsu Semiconductor Ltd | 半導体装置の製造方法 |
Families Citing this family (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6030874A (en) * | 1997-01-21 | 2000-02-29 | Texas Instruments Incorporated | Doped polysilicon to retard boron diffusion into and through thin gate dielectrics |
| US5891782A (en) * | 1997-08-21 | 1999-04-06 | Sharp Microelectronics Technology, Inc. | Method for fabricating an asymmetric channel doped MOS structure |
| TW388087B (en) * | 1997-11-20 | 2000-04-21 | Winbond Electronics Corp | Method of forming buried-channel P-type metal oxide semiconductor |
| US6013546A (en) * | 1997-12-19 | 2000-01-11 | Advanced Micro Devices, Inc. | Semiconductor device having a PMOS device with a source/drain region formed using a heavy atom p-type implant and method of manufacture thereof |
| US6146934A (en) * | 1997-12-19 | 2000-11-14 | Advanced Micro Devices, Inc. | Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof |
| KR100248509B1 (ko) * | 1997-12-30 | 2000-03-15 | 김영환 | 매몰 채널 nmos 트랜지스터를 구비하는 반도체 장치의cmos 논리 게이트 및 그 제조방법 |
| WO1999035685A1 (en) * | 1998-01-05 | 1999-07-15 | Advanced Micro Devices, Inc. | Integrated cmos transistor formation |
| US6063682A (en) * | 1998-03-27 | 2000-05-16 | Advanced Micro Devices, Inc. | Ultra-shallow p-type junction having reduced sheet resistance and method for producing shallow junctions |
| US6331456B1 (en) * | 1998-05-04 | 2001-12-18 | Texas Instruments - Acer Incorporated | Fipos method of forming SOI CMOS structure |
| US6087209A (en) * | 1998-07-31 | 2000-07-11 | Advanced Micro Devices, Inc. | Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant |
| US6180468B1 (en) * | 1998-10-23 | 2001-01-30 | Advanced Micro Devices Inc. | Very low thermal budget channel implant process for semiconductors |
| FR2794898B1 (fr) | 1999-06-11 | 2001-09-14 | France Telecom | Dispositif semi-conducteur a tension de seuil compensee et procede de fabrication |
| KR100332107B1 (ko) * | 1999-06-29 | 2002-04-10 | 박종섭 | 반도체 소자의 트랜지스터 제조 방법 |
| US6372582B1 (en) * | 1999-08-18 | 2002-04-16 | Advanced Micro Devices, Inc. | Indium retrograde channel doping for improved gate oxide reliability |
| US6686629B1 (en) * | 1999-08-18 | 2004-02-03 | International Business Machines Corporation | SOI MOSFETS exhibiting reduced floating-body effects |
| US20030235936A1 (en) * | 1999-12-16 | 2003-12-25 | Snyder John P. | Schottky barrier CMOS device and method |
| US6303479B1 (en) * | 1999-12-16 | 2001-10-16 | Spinnaker Semiconductor, Inc. | Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts |
| JP2002076332A (ja) * | 2000-08-24 | 2002-03-15 | Hitachi Ltd | 絶縁ゲート型電界効果トランジスタ及びその製造方法 |
| JP3940565B2 (ja) * | 2001-03-29 | 2007-07-04 | 株式会社東芝 | 半導体装置及びその製造方法 |
| EP1417718A1 (en) * | 2001-08-10 | 2004-05-12 | Spinnaker Semiconductor, Inc. | Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate |
| US20060079059A1 (en) * | 2001-08-10 | 2006-04-13 | Snyder John P | Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate |
| JP3481223B2 (ja) * | 2001-09-07 | 2003-12-22 | 松下電器産業株式会社 | 半導体装置の製造方法 |
| US6747318B1 (en) * | 2001-12-13 | 2004-06-08 | Lsi Logic Corporation | Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides |
| US6974737B2 (en) * | 2002-05-16 | 2005-12-13 | Spinnaker Semiconductor, Inc. | Schottky barrier CMOS fabrication method |
| US6756619B2 (en) * | 2002-08-26 | 2004-06-29 | Micron Technology, Inc. | Semiconductor constructions |
| EP1554756B1 (en) * | 2002-09-20 | 2016-07-20 | Koninklijke Philips N.V. | A method for manufacturing an electrical device |
| KR100496551B1 (ko) * | 2002-11-20 | 2005-06-22 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
| KR100460757B1 (ko) * | 2003-04-30 | 2004-12-14 | 주식회사 하이닉스반도체 | 이중 도핑 구조의 초박형 에피채널 반도체 소자의 제조 방법 |
| US7282782B2 (en) * | 2004-03-12 | 2007-10-16 | Hewlett-Packard Development Company, L.P. | Combined binary oxide semiconductor device |
| US8314420B2 (en) * | 2004-03-12 | 2012-11-20 | Hewlett-Packard Development Company, L.P. | Semiconductor device with multiple component oxide channel |
| KR100596851B1 (ko) * | 2004-09-02 | 2006-07-05 | 주식회사 하이닉스반도체 | 반도체 소자의 셀 채널 이온 주입 방법 |
| JP5114829B2 (ja) * | 2005-05-13 | 2013-01-09 | ソニー株式会社 | 半導体装置およびその製造方法 |
| KR100779395B1 (ko) * | 2006-08-31 | 2007-11-23 | 동부일렉트로닉스 주식회사 | 반도체소자 및 그 제조방법 |
| US20090032885A1 (en) * | 2007-07-31 | 2009-02-05 | Intersil Americas, Inc. | Buried Isolation Layer |
| JP2009182089A (ja) * | 2008-01-30 | 2009-08-13 | Panasonic Corp | 半導体装置の製造方法 |
| TWI487104B (zh) * | 2008-11-07 | 2015-06-01 | Semiconductor Energy Lab | 半導體裝置和其製造方法 |
| US8404551B2 (en) * | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
| CN105679712A (zh) * | 2015-12-31 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | Sonos器件的工艺方法 |
| US10553494B2 (en) * | 2016-11-29 | 2020-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Breakdown resistant semiconductor apparatus and method of making same |
| JP6996858B2 (ja) * | 2017-03-29 | 2022-01-17 | 旭化成エレクトロニクス株式会社 | 半導体装置及びその製造方法 |
| US10319855B2 (en) | 2017-09-25 | 2019-06-11 | International Business Machines Corporation | Reducing series resistance between source and/or drain regions and a channel region |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5413779A (en) * | 1977-07-04 | 1979-02-01 | Toshiba Corp | Semiconductor integrated circuit device |
| US4199773A (en) * | 1978-08-29 | 1980-04-22 | Rca Corporation | Insulated gate field effect silicon-on-sapphire transistor and method of making same |
| US4574467A (en) * | 1983-08-31 | 1986-03-11 | Solid State Scientific, Inc. | N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel |
| US4679303A (en) * | 1983-09-30 | 1987-07-14 | Hughes Aircraft Company | Method of fabricating high density MOSFETs with field aligned channel stops |
| US5256583A (en) * | 1986-03-21 | 1993-10-26 | Advanced Power Technology, Inc. | Mask surrogate semiconductor process with polysilicon gate protection |
| EP0296627A3 (en) * | 1987-06-25 | 1989-10-18 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device |
| US4845047A (en) * | 1987-06-25 | 1989-07-04 | Texas Instruments Incorporated | Threshold adjustment method for an IGFET |
| US5114874A (en) * | 1987-07-15 | 1992-05-19 | Rockwell International Corporation | Method of making a sub-micron NMOS, PMOS and CMOS devices with methods for forming sub-micron contacts |
| JPH0744275B2 (ja) * | 1988-10-06 | 1995-05-15 | 日本電気株式会社 | 高耐圧mos型半導体装置の製造方法 |
| JPH02291150A (ja) * | 1989-04-28 | 1990-11-30 | Hitachi Ltd | 半導体装置 |
| US5134448A (en) * | 1990-01-29 | 1992-07-28 | Motorola, Inc. | MOSFET with substrate source contact |
| JPH0734477B2 (ja) * | 1990-05-28 | 1995-04-12 | 株式会社東芝 | 半導体装置の製造方法 |
| US5266510A (en) * | 1990-08-09 | 1993-11-30 | Micron Technology, Inc. | High performance sub-micron p-channel transistor with germanium implant |
| KR940002400B1 (ko) * | 1991-05-15 | 1994-03-24 | 금성일렉트론 주식회사 | 리세스 게이트를 갖는 반도체장치의 제조방법 |
| US5401994A (en) * | 1991-05-21 | 1995-03-28 | Sharp Kabushiki Kaisha | Semiconductor device with a non-uniformly doped channel |
| US5244823A (en) * | 1991-05-21 | 1993-09-14 | Sharp Kabushiki Kaisha | Process for fabricating a semiconductor device |
| US5320974A (en) * | 1991-07-25 | 1994-06-14 | Matsushita Electric Industrial Co., Ltd. | Method for making semiconductor transistor device by implanting punch through stoppers |
| US5266508A (en) * | 1991-08-26 | 1993-11-30 | Sharp Kabushiki Kaisha | Process for manufacturing semiconductor device |
| US5330925A (en) * | 1992-06-18 | 1994-07-19 | At&T Bell Laboratories | Method for making a MOS device |
| US5346587A (en) * | 1993-08-12 | 1994-09-13 | Micron Semiconductor, Inc. | Planarization of a gate electrode for improved gate patterning over non-planar active area isolation |
-
1995
- 1995-02-11 TW TW084101220A patent/TW304301B/zh active
- 1995-06-07 US US08/478,133 patent/US5710055A/en not_active Expired - Lifetime
- 1995-11-27 CN CN95120272A patent/CN1132941A/zh active Pending
- 1995-11-30 KR KR1019950045754A patent/KR960026938A/ko not_active Abandoned
- 1995-12-01 DE DE19544945A patent/DE19544945A1/de not_active Withdrawn
- 1995-12-01 JP JP7335700A patent/JPH08227992A/ja active Pending
-
1996
- 1996-05-24 US US08/656,996 patent/US5767557A/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012028534A (ja) * | 2010-07-22 | 2012-02-09 | Fujitsu Semiconductor Ltd | 半導体装置の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1132941A (zh) | 1996-10-09 |
| DE19544945A1 (de) | 1996-06-13 |
| KR960026938A (ko) | 1996-07-22 |
| US5767557A (en) | 1998-06-16 |
| US5710055A (en) | 1998-01-20 |
| TW304301B (enExample) | 1997-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH08227992A (ja) | Pmosfet半導体デバイス | |
| KR100414736B1 (ko) | 반도체소자의 트랜지스터 형성방법 | |
| KR900000072B1 (ko) | 협채널 폭을 갖는 절연게이트형 fet의 제조방법 | |
| US6316302B1 (en) | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant | |
| US7939902B2 (en) | Field effect transistor having source and/or drain forming schottky or schottky-like contact with strained semiconductor substrate | |
| EP0631689A4 (en) | THRESHOLD TUNING IN VERTICAL DMOS ARRANGEMENTS. | |
| EP1121716A2 (en) | Elevated channel mosfet | |
| JPH08250728A (ja) | 電界効果型半導体装置及びその製造方法 | |
| JPH10178104A (ja) | Cmosfet製造方法 | |
| KR910003835B1 (ko) | Mis형 반도체장치와 그 제조방법 | |
| JP3200231B2 (ja) | 半導体装置の製造方法 | |
| US6624476B1 (en) | Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer and method of fabricating | |
| US7163878B2 (en) | Ultra-shallow arsenic junction formation in silicon germanium | |
| KR100556350B1 (ko) | 반도체 소자 및 그 제조방법 | |
| JPH04218925A (ja) | 半導体装置およびその製造方法 | |
| US5612244A (en) | Insulated gate semiconductor device having a cavity under a portion of a gate structure and method of manufacture | |
| JP3206419B2 (ja) | 半導体装置の製造方法 | |
| KR100214297B1 (ko) | 반도체장치의 제조방법 | |
| JP3052348B2 (ja) | 半導体装置の製造方法 | |
| JPH113996A (ja) | 半導体装置及びその製造方法 | |
| JP2506947B2 (ja) | 半導体装置およびその製造方法 | |
| JPH04330782A (ja) | 微細半導体装置およびその製造方法 | |
| JPH07122741A (ja) | 半導体装置の製造方法 | |
| JPH05343677A (ja) | 半導体装置および製造方法 | |
| JPH05226595A (ja) | 相補型misトランジスタ装置 |