JPH0783119B2 - 電界効果トランジスタ - Google Patents

電界効果トランジスタ

Info

Publication number
JPH0783119B2
JPH0783119B2 JP63211858A JP21185888A JPH0783119B2 JP H0783119 B2 JPH0783119 B2 JP H0783119B2 JP 63211858 A JP63211858 A JP 63211858A JP 21185888 A JP21185888 A JP 21185888A JP H0783119 B2 JPH0783119 B2 JP H0783119B2
Authority
JP
Japan
Prior art keywords
semiconductor region
region
semiconductor
effect transistor
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63211858A
Other languages
English (en)
Other versions
JPH0260169A (ja
Inventor
千鶴 香山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63211858A priority Critical patent/JPH0783119B2/ja
Priority to US07/397,232 priority patent/US4952991A/en
Priority to EP89308664A priority patent/EP0358389A1/en
Publication of JPH0260169A publication Critical patent/JPH0260169A/ja
Publication of JPH0783119B2 publication Critical patent/JPH0783119B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電界効果トランジスタに関し、特に絶縁ゲート
型電界効果トランジスタに関する。
〔従来の技術〕
従来この種の技術は、第４図に示すようにＮ型半導体基
板１にN-型のエピタキシャル層２を成長させ、Ｐ型不純
物を選択的にイオン注入し、押し込み、P-型領域３を作
り、このP-型領域３内に、N+ソース層4,P+層７を形成
し、ゲート電極6,ソース電極10を設け、裏面にドレイン
電極11を有する構造となっていた。
〔発明が解決しようとする課題〕 上述した従来の絶縁ゲート型電界効果トランジスタはド
レイン領域の表層部がN-型エピタキシャル成長層２とな
っているので、不純物濃度が低くなっている。
ソース領域４から流出した電子は、ドレイン領域の表層
部を通過してドレイン電極11に至るので、ドレイン領域
の不純物濃度は、オン抵抗等に影響するという問題があ
る。
本発明の目的は、耐圧低下をすることなくオン抵抗を低
減させる構造を持つ絶縁ゲート型電界効果トランジスタ
を提供することにある。
〔課題を解決するための手段〕
本発明によれば、一導電型の半導体基板の一主面に対向
する領域を有するように設けられた他の導電型の第１の
半導体領域と、第１の半導体領域の対向する領域間の一
主面に第１の半導体領域と接して設けられた一導電型で
半導体基板より高濃度の第２の半導体領域と、第２の半
導体内に設けられた他の導電型の第３の半導体領域と、
第１の半導体領域内の一主面に第２の半導体領域と離間
に設けられた一導電型の第４の半導体領域と、第２の半
導体領域と第４の半導体領域間の第１の半導体領域上に
設けられたゲート電極と、第２の半導体領域及び第３の
半導体領域上に設けられた絶縁膜と、第４の半導体領域
と電気的に接続されて設けられた第１の電極と、半導体
基板の他の主面と電気的に接続して設けられた第２の電
極とを有する電界効果トランジスタが得られる。
〔実施例〕
次に、本発明について図面を参照して説明する。
第１図は本発明をＮチャネル型絶縁ゲート電界効果トラ
ンジスタに適用した一実施例の断面図である。第２図
（ａ），（ｂ），（ｃ），（ｄ）は本発明の絶縁ゲート
電界効果トランジスタを形成するための主な工程におけ
る断面図である。
まず、第２図（ａ）に示すように、Ｎ型半導体基板１上
にN-型エピタキシャル成長層２を成長させＰ型不純物を
酸化膜９をマスクとして、選択的にイオン注入し押し込
みを行いP-領域３を形成させる。次に同一マスクでN+ソ
ース領域４を形成するためにＮ型不純物を高濃度でイオ
ン注入する。
次に、第２図（ｂ）に示すように、別の酸化膜21をマス
クとし、ドレイン領域表層部５にＮ型不純物を高濃度で
イオン注入する。
次に、第２図（ｃ）に示すように、ポイシリコン層６を
マスクとしてＰ型不純物を高濃度でイオン注入してP+層
7,8を形成する。
次に、第２図（ｄ）に示すように、押し込みを行い、適
当な拡散深さを得、その後ドレイン領域上に酸化膜29を
形成させ、ソース電極10を設け裏面にドレイン電極11を
付する。
第３図は、本実施例の絶縁電界効果トランジスタ動作時
の電子の動き及び空乏層の拡がりを示したものである。
N+ソース領域４より流れた電子はチャネル12,ドレイン
領域表層部５を通過し、ドレイン電極11に至る。ドレイ
ン領域表層部５は、P-領域３形成後の高濃度不純物イオ
ン注入によるものであり、ドーズ量はP+層８（５×1014
/cm2〜５×1016/cm2）＞ドレイン領域表層部５（２×10
11/cm2〜５×1014/cm2）＞P-領域３とするため押し込み
によって、ドレイン領域表層部５はP-領域３に横方向に
拡散する。このためチャネル12は短くなり、又、ドレイ
ン領域表層部５が高濃度であるため、オン抵抗が低下す
る。
さらに、ドレイン領域のP+層８は、浮遊状態にあり、フ
ィールドリング同様、空乏層が拡がり、ゲート電極６下
の電界集中が緩和され耐圧の低下を防ぐことができる。
なお、本実施例においては、Ｎチャネル型の電界効果ト
ランジスタについて説明したが、導電型を反対にしてＰ
チャネル型としても同様の効果が得られる。
〔発明の効果〕
以上説明したように本発明は、絶縁ゲート型電界効果ト
ランジスタにおいて、ベース領域形成後ドレイン表層部
を高濃度とし、ドレイン領域の一部にドレイン領域と反
対の導電型領域を形成させることによって、耐圧の低下
なしにオン抵抗を低減させるという効果がある。
【図面の簡単な説明】
第１図は本発明の一実施例の断面図、第２図（ａ）〜
（ｄ）は本発明の一実施例を形成するための主な工程を
示す断面図、第３図は第１図に示した一実施例の動作時
の電子の動き及び空乏層の拡がりを示す断面図、第４図
は従来の絶縁ゲート型電界効果トランジスタの断面図で
ある。 １……Ｎ型半導体基板、２……N-型エピタキシャル成長
層、３……P-型領域（ベース領域）、４……N+ソース
層、５……ドレイン領域表層部、６……ポリシリコン層
（ゲート電極）、７……P+層、８……P+層、９……酸化
膜、10……ソース電極、11……ドレイン電極、12……チ
ャネル。

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】一導電型の半導体基板の一主面に選択的に
    設けられた他の導電型の複数の第１の半導体領域と、互
    いに対向する第１の半導体領域間の前記一主面に該第１
    の半導体領域と接して設けられた前記一導電型で前記半
    導体基板より高濃度の第２の半導体領域と、該第２の半
    導体領域内に少なくともその底部が前記半導体基板に接
    するように設けられた前記他の導電型の第３の半導体領
    域と、前記第１の半導体領域内の前記一主面に前記第２
    の半導体領域と離間して設けられた前記一導電型の第４
    の半導体領域と、前記第２の半導体領域と前記第４の半
    導体領域間の前記第１の半導体領域上に設けられたゲー
    ト電極と、前記第２の半導体領域及び前記第３の半導体
    領域上に設けられた絶縁膜と、前記第４の半導体領域と
    電気的に接続されて設けられた第１の電極と、前記半導
    体基板の他の主面と電気的に接続して設けられた第２の
    電極とを有することを特徴とする電界効果トランジス
    タ。
JP63211858A 1988-08-25 1988-08-25 電界効果トランジスタ Expired - Lifetime JPH0783119B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP63211858A JPH0783119B2 (ja) 1988-08-25 1988-08-25 電界効果トランジスタ
US07/397,232 US4952991A (en) 1988-08-25 1989-08-23 Vertical field-effect transistor having a high breakdown voltage and a small on-resistance
EP89308664A EP0358389A1 (en) 1988-08-25 1989-08-25 Vertical field-effect transistor having a high breakdown voltage and a small on-resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63211858A JPH0783119B2 (ja) 1988-08-25 1988-08-25 電界効果トランジスタ

Publications (2)

Publication Number Publication Date
JPH0260169A JPH0260169A (ja) 1990-02-28
JPH0783119B2 true JPH0783119B2 (ja) 1995-09-06

Family

ID=16612766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63211858A Expired - Lifetime JPH0783119B2 (ja) 1988-08-25 1988-08-25 電界効果トランジスタ

Country Status (3)

Country Link
US (1) US4952991A (ja)
EP (1) EP0358389A1 (ja)
JP (1) JPH0783119B2 (ja)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072268A (en) * 1991-03-12 1991-12-10 Power Integrations, Inc. MOS gated bipolar transistor
US5243234A (en) * 1991-03-20 1993-09-07 Industrial Technology Research Institute Dual gate LDMOSFET device for reducing on state resistance
US5243211A (en) * 1991-11-25 1993-09-07 Harris Corporation Power fet with shielded channels
US5506421A (en) * 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
JP2689874B2 (ja) * 1993-12-17 1997-12-10 関西日本電気株式会社 高耐圧ｍｏｓトランジスタ
US5719421A (en) * 1994-10-13 1998-02-17 Texas Instruments Incorporated DMOS transistor with low on-resistance and method of fabrication
EP0729186B1 (en) * 1995-02-24 1999-05-06 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno MOS-technology power device integrated structure and manufacturing process thereof
US5798554A (en) * 1995-02-24 1998-08-25 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno MOS-technology power device integrated structure and manufacturing process thereof
US5777371A (en) * 1995-09-29 1998-07-07 Kabushiki Kaisha Toshiba High-breakdown-voltage semiconductor device
DE69531783T2 (de) * 1995-10-09 2004-07-15 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno - Corimme Herstellungsverfahren für Leistungsanordnung mit Schutzring
JP3279151B2 (ja) * 1995-10-23 2002-04-30 トヨタ自動車株式会社 半導体装置及びその製造方法
DE69533134T2 (de) * 1995-10-30 2005-07-07 Stmicroelectronics S.R.L., Agrate Brianza Leistungsbauteil hoher Dichte in MOS-Technologie
EP0772242B1 (en) 1995-10-30 2006-04-05 STMicroelectronics S.r.l. Single feature size MOS technology power device
US6228719B1 (en) 1995-11-06 2001-05-08 Stmicroelectronics S.R.L. MOS technology power device with low output resistance and low capacitance, and related manufacturing process
DE69515876T2 (de) * 1995-11-06 2000-08-17 St Microelectronics Srl Leistungsbauelement in MOS-Technologie mit niedrigem Ausgangswiderstand und geringer Kapazität und dessen Herstellungsverfahren
DE69518653T2 (de) * 1995-12-28 2001-04-19 St Microelectronics Srl MOS-Technologie-Leistungsanordnung in integrierter Struktur
US5719409A (en) * 1996-06-06 1998-02-17 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
US6147362A (en) * 1997-03-17 2000-11-14 Honeywell International Inc. High performance display pixel for electronics displays
EP0961325B1 (en) 1998-05-26 2008-05-07 STMicroelectronics S.r.l. High integration density MOS technology power device
US6617643B1 (en) * 2002-06-28 2003-09-09 Mcnc Low power tunneling metal-oxide-semiconductor (MOS) device
US8354310B2 (en) * 2010-07-06 2013-01-15 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences SOI MOS device having a source/body ohmic contact and manufacturing method thereof
JP2015056472A (ja) * 2013-09-11 2015-03-23 株式会社東芝 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53135284A (en) * 1977-04-30 1978-11-25 Nec Corp Production of field effect transistor
US4593302B1 (en) * 1980-08-18 1998-02-03 Int Rectifier Corp Process for manufacture of high power mosfet laterally distributed high carrier density beneath the gate oxide
DE3346286A1 (de) * 1982-12-21 1984-06-28 International Rectifier Corp., Los Angeles, Calif. Hochleistungs-metalloxid-feldeffekttransistor- halbleiterbauteil
JPS59167066A (ja) * 1983-03-14 1984-09-20 Nissan Motor Co Ltd 縦形ｍｏｓｆｅｔ
JPS60262468A (ja) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd Ｍｏｓ型電界効果トランジスタ
JPS61150378A (ja) * 1984-12-25 1986-07-09 Toshiba Corp 電界効果トランジスタ
JPS6211275A (ja) * 1986-07-18 1987-01-20 Hitachi Ltd 半導体装置
EP0279403A3 (en) * 1987-02-16 1988-12-07 Nec Corporation Vertical mos field effect transistor having a high withstand voltage and a high switching speed

Also Published As

Publication number Publication date
JPH0260169A (ja) 1990-02-28
US4952991A (en) 1990-08-28
EP0358389A1 (en) 1990-03-14

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