JPH0746507B2 - 二重ポート読出し／書込みメモリー - Google Patents

二重ポート読出し／書込みメモリー

Info

Publication number
JPH0746507B2
JPH0746507B2 JP1329411A JP32941189A JPH0746507B2 JP H0746507 B2 JPH0746507 B2 JP H0746507B2 JP 1329411 A JP1329411 A JP 1329411A JP 32941189 A JP32941189 A JP 32941189A JP H0746507 B2 JPH0746507 B2 JP H0746507B2
Authority
JP
Japan
Prior art keywords
write
data
ram
read
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1329411A
Other languages
English (en)
Japanese (ja)
Other versions
JPH02220293A (ja
Inventor
デービッド・イー・クッシング
ロメオ・クハリレー
ジアン―クオ・シェン
ミン―ツザー・ミウ
Original Assignee
ブル・エッチエヌ・インフォメーション・システムズ・インコーポレーテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ブル・エッチエヌ・インフォメーション・システムズ・インコーポレーテッド filed Critical ブル・エッチエヌ・インフォメーション・システムズ・インコーポレーテッド
Publication of JPH02220293A publication Critical patent/JPH02220293A/ja
Publication of JPH0746507B2 publication Critical patent/JPH0746507B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
  • Dram (AREA)
  • Executing Machine-Instructions (AREA)
JP1329411A 1988-12-19 1989-12-19 二重ポート読出し／書込みメモリー Expired - Lifetime JPH0746507B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US286552 1988-12-19
US07/286,552 US4933909A (en) 1988-12-19 1988-12-19 Dual read/write register file memory

Publications (2)

Publication Number Publication Date
JPH02220293A JPH02220293A (ja) 1990-09-03
JPH0746507B2 true JPH0746507B2 (ja) 1995-05-17

Family

ID=23099119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1329411A Expired - Lifetime JPH0746507B2 (ja) 1988-12-19 1989-12-19 二重ポート読出し／書込みメモリー

Country Status (9)

Country Link
US (1) US4933909A (ko)
EP (1) EP0374829B1 (ko)
JP (1) JPH0746507B2 (ko)
KR (1) KR930004426B1 (ko)
AU (1) AU626363B2 (ko)
CA (1) CA2005953A1 (ko)
DE (1) DE68922975T2 (ko)
DK (1) DK648089A (ko)
YU (1) YU240389A (ko)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770213B2 (ja) * 1988-10-03 1995-07-31 三菱電機株式会社 半導体メモリ装置
US5107462A (en) * 1989-02-03 1992-04-21 Digital Equipment Corporation Self timed register file having bit storage cells with emitter-coupled output selectors for common bits sharing a common pull-up resistor and a common current sink
US5261064A (en) * 1989-10-03 1993-11-09 Advanced Micro Devices, Inc. Burst access memory
US5115411A (en) * 1990-06-06 1992-05-19 Ncr Corporation Dual port memory system
JP2573395B2 (ja) * 1990-06-11 1997-01-22 株式会社東芝 デュアルポートメモリ装置
JPH05503390A (ja) * 1990-10-26 1993-06-03 マイクロン・テクノロジー・インコーポレイテッド 同時読み書き機能およびクロック歪みに対する耐性を有する高速５ポートレジスタファイル
JPH04184788A (ja) * 1990-11-20 1992-07-01 Fujitsu Ltd 半導体記憶装置
US5249283A (en) * 1990-12-24 1993-09-28 Ncr Corporation Cache coherency method and apparatus for a multiple path interconnection network
JP3169639B2 (ja) * 1991-06-27 2001-05-28 日本電気株式会社 半導体記憶装置
US5257236A (en) * 1991-08-01 1993-10-26 Silicon Engineering, Inc. Static RAM
US5321809A (en) * 1992-09-11 1994-06-14 International Business Machines Corporation Categorized pixel variable buffering and processing for a graphics system
US5315178A (en) * 1993-08-27 1994-05-24 Hewlett-Packard Company IC which can be used as a programmable logic cell array or as a register file
US5581720A (en) * 1994-04-15 1996-12-03 David Sarnoff Research Center, Inc. Apparatus and method for updating information in a microcode instruction
US5751999A (en) * 1994-06-23 1998-05-12 Matsushita Electric Industrial Co., Ltd. Processor and data memory for outputting and receiving data on different buses for storage in the same location
US5745732A (en) * 1994-11-15 1998-04-28 Cherukuri; Ravikrishna V. Computer system including system controller with a write buffer and plural read buffers for decoupled busses
US5566123A (en) 1995-02-10 1996-10-15 Xilinx, Inc. Synchronous dual port ram
US5813037A (en) * 1995-03-30 1998-09-22 Intel Corporation Multi-port register file for a reservation station including a pair of interleaved storage cells with shared write data lines and a capacitance isolation mechanism
US5713039A (en) * 1995-12-05 1998-01-27 Advanced Micro Devices, Inc. Register file having multiple register storages for storing data from multiple data streams
KR100190373B1 (ko) * 1996-02-08 1999-06-01 김영환 리드 패스를 위한 고속 동기식 메모리 장치
US5802579A (en) * 1996-05-16 1998-09-01 Hughes Electronics Corporation System and method for simultaneously reading and writing data in a random access memory
US5987578A (en) * 1996-07-01 1999-11-16 Sun Microsystems, Inc. Pipelining to improve the interface of memory devices
US5923608A (en) * 1997-10-31 1999-07-13 Vlsi Technology, Inc. Scalable N-port memory structures
US6360307B1 (en) 1998-06-18 2002-03-19 Cypress Semiconductor Corporation Circuit architecture and method of writing data to a memory
US7400548B2 (en) * 2005-02-09 2008-07-15 International Business Machines Corporation Method for providing multiple reads/writes using a 2read/2write register file array
US7962698B1 (en) 2005-10-03 2011-06-14 Cypress Semiconductor Corporation Deterministic collision detection
JP4201011B2 (ja) * 2006-03-27 2008-12-24 トヨタ自動車株式会社 蓄熱装置
CN102110464B (zh) * 2009-12-26 2015-06-10 上海芯豪微电子有限公司 宽带读写存储器装置
US8862836B2 (en) * 2011-06-14 2014-10-14 Texas Instruments Incorporated Multi-port register file with an input pipelined architecture with asynchronous reads and localized feedback
US8862835B2 (en) * 2011-06-14 2014-10-14 Texas Instruments Incorporated Multi-port register file with an input pipelined architecture and asynchronous read data forwarding

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4287575A (en) * 1979-12-28 1981-09-01 International Business Machines Corporation High speed high density, multi-port random access memory cell
JPS573155A (en) * 1980-06-05 1982-01-08 Ricoh Co Ltd Input and output control circuit for memory device
US4628489A (en) * 1983-10-03 1986-12-09 Honeywell Information Systems Inc. Dual address RAM
US4610004A (en) * 1984-10-10 1986-09-02 Advanced Micro Devices, Inc. Expandable four-port register file
US4623990A (en) * 1984-10-31 1986-11-18 Advanced Micro Devices, Inc. Dual-port read/write RAM with single array
US4811296A (en) * 1987-05-15 1989-03-07 Analog Devices, Inc. Multi-port register file with flow-through of data

Also Published As

Publication number Publication date
EP0374829B1 (en) 1995-06-07
JPH02220293A (ja) 1990-09-03
DK648089D0 (da) 1989-12-19
YU240389A (sh) 1994-01-20
CA2005953A1 (en) 1990-06-19
DE68922975D1 (de) 1995-07-13
EP0374829A2 (en) 1990-06-27
AU626363B2 (en) 1992-07-30
DE68922975T2 (de) 1996-03-21
KR900010561A (ko) 1990-07-07
DK648089A (da) 1990-06-20
KR930004426B1 (ko) 1993-05-27
US4933909A (en) 1990-06-12
AU4692089A (en) 1990-06-21
EP0374829A3 (en) 1991-05-29

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