JPH0582745B2 - - Google Patents

Info

Publication number
JPH0582745B2
JPH0582745B2 JP59098241A JP9824184A JPH0582745B2 JP H0582745 B2 JPH0582745 B2 JP H0582745B2 JP 59098241 A JP59098241 A JP 59098241A JP 9824184 A JP9824184 A JP 9824184A JP H0582745 B2 JPH0582745 B2 JP H0582745B2
Authority
JP
Japan
Prior art keywords
alloy
copper
sealing
lead frame
composite material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59098241A
Other languages
English (en)
Other versions
JPS60242653A (ja
Inventor
Teruo Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Daido Steel Co Ltd
Original Assignee
Daido Steel Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Daido Steel Co Ltd filed Critical Daido Steel Co Ltd
Priority to JP59098241A priority Critical patent/JPS60242653A/ja
Publication of JPS60242653A publication Critical patent/JPS60242653A/ja
Publication of JPH0582745B2 publication Critical patent/JPH0582745B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Description

【発明の詳細な説明】 【産業上の利用分野】
本発明は、セラミツクパツケージICのリード
フレームに用いる材料に関する。
【従来の技術】
セラミツクパツケージICのリードフレームと
しては、熱膨脹率が低融点ガラスのそれに類似の
材料が使用されており、その代表は「42合金」と
よばれる42%Ni−Fe合金、および「コバール」
の名がある29%Ni−12%Co−Fe合金である。 これらの合金の欠点は、電気伝導度が3%
IACSときわめて低く、これに比例して、熱伝導
率も0.04cal/cmsec℃以下と低いことであつて、
この材料でつくつたリードフレームは、ICチツ
プにおいて発生した熱を伝導拡散するはたらきが
乏しい。とくに、最近の傾向はICの集積度をさ
らに高める方向に進んでいるので、ICチツプに
おける発熱は増大し、その除去はますます大きな
問題となつている。
【発明が解決しようとする課題】
従つて、熱伝導率および電気伝導率ができるだ
け高く、しかも熱膨脹係数はセラミツクやガラス
と同等にしたリードフレーム用の材料が求められ
ている。本発明の目的は、この要求にこたえる材
料を提供することにある。
【課題を解決するための手段】
本発明のリードフレーム用の材料は、熱伝導度
および電気伝導度が大きい材料と、熱膨脹係数が
適正なレベルにある材料とを複合することにより
上記の要求をみたしたものである。 本発明のリードフレーム用複合材は、熱膨脹係
数が(50〜90)×10-7/℃(30〜450℃)の封着合
金の板の平面方向の少なくとも一方の縁に、電気
伝導率が14%IACA以上の銅または銅合金の板を
接合してなる。 本発明のリードフレーム用複合材の態様は、第
1図AおよびBにみるとおりである。Aは封着合
金の板12の平面方向の一方の縁に銅または銅合
金の板11の縁を接合した複合材1Aを示し、B
は板12の平面方向の両方の縁に板11を接合し
た複合材1Bを示す。 二種の金属板の縁を接合するには、電子ビーム
溶接などの手段が利用できる。
【作用】
電気伝導度が14%IACA以上の銅または銅合金
は、熱伝導率が高いからICチツプからの熱の放
散を促進し、一方、熱膨脹係数が(50〜90)×
10-7/℃の封着合金は、ガラスまたはセラミツク
のシール材料との接着を良好に保つ役割りを担
う。このようにして、高い熱伝導と適当な膨脹と
いう二つの要求が、同時にみたされるわけであ
る。
【実施例】
本発明のリードフレーム用材料を使用したIC
の例を、第2図および第3図に示す。 第2図のICはサーテツプ型のものであつて、
ICチツプ2をセラミツク製の上下のパツケージ
3Aおよび3B内におさめ、リードフレーム1を
低融点の封着ガラス4で封入シーリングしてあ
る。リードフレーム1は、第1図A,Bに示す構
成のものである。なお、リードフレーム1とIC
チツプの電極との間はAl線5で接続してあり、
このためにリードフレームの端にはAlの箔がク
ラツドしてある。 第3図のICは積層型のものであつて、ICチツ
プ2をセラミツクパツケージ3Aおよび3B内に
封入するのに、ガラスを使わずにロウ材6でロウ
付けしてある。リードフレーム1も、やはりロウ
材6でロウ付けされている。 これらの実施例から明らかなように、接合する
封着合金の板と銅または銅合金の板の寸法の相互
関係は、ICのタイプや形状寸法に応じて、任意
に選択することができる。
【発明の効果】
本発明の複合材からなるリードフレームは、前
記のように高い熱伝導と良好なセラミツク封着性
とを兼ねそなえているから、ICの高密度化の要
請にこたえ、しかも確実な封入シーリングを行な
うことができる。熱伝導度向上の効果は、封着合
金と接合する銅または銅合金の板の寸法を適切に
えらぶことにより、最大にすることができる。
【図面の簡単な説明】
第1図AおよびBは、ともに本発明のリードフ
レーム用複合材の態様を示す拡大断面図である。
第2図および第3図は、いずれも本発明の複合材
からなるリードフレームを用いて製作したセラミ
ツクパツケージICの構造を示す、模式的な拡大
断面図である。 1,1A,1B……リードフレーム用複合材、
1……リードフレーム、11……銅または銅合
金、12……封着合金、2……ICチツプ、3A,
3B……セラミツクパツケージ、4……封着ガラ
ス、6……ロウ材。

Claims (1)

  1. 【特許請求の範囲】 1 熱膨脹係数が(50〜90)×10-7/℃(30〜450
    ℃)の封着合金の板の平面方向の少なくとも一方
    の縁に、電気伝導率が14%IACS以上の銅または
    銅合金の板を接合してなるリードフレーム用複合
    材。 2 封着合金として、42%Ni−Fe合金または29
    %Ni−17%Co−Fe合金を使用した特許請求の範
    囲第1項に記載の複合材。
JP59098241A 1984-05-16 1984-05-16 リ−ドフレ−ム用複合材 Granted JPS60242653A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59098241A JPS60242653A (ja) 1984-05-16 1984-05-16 リ−ドフレ−ム用複合材

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59098241A JPS60242653A (ja) 1984-05-16 1984-05-16 リ−ドフレ−ム用複合材

Publications (2)

Publication Number Publication Date
JPS60242653A JPS60242653A (ja) 1985-12-02
JPH0582745B2 true JPH0582745B2 (ja) 1993-11-22

Family

ID=14214462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59098241A Granted JPS60242653A (ja) 1984-05-16 1984-05-16 リ−ドフレ−ム用複合材

Country Status (1)

Country Link
JP (1) JPS60242653A (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217649A (ja) * 1986-03-18 1987-09-25 Kyocera Corp 混成集積回路素子収納用パツケ−ジ
JPS6489552A (en) * 1987-09-30 1989-04-04 Toshiba Corp Ceramic substrate
JPH02109357A (ja) * 1988-10-18 1990-04-23 Sumitomo Special Metals Co Ltd プラスチックモールド用クラッド板の製造方法
JPH03218660A (ja) * 1989-08-25 1991-09-26 Kyocera Corp 半導体素子収納用パッケージ
JPH07109869B2 (ja) * 1989-12-01 1995-11-22 日立金属株式会社 リードフレーム用部材
JPH03188659A (ja) * 1989-12-19 1991-08-16 Toppan Printing Co Ltd 半導体集積回路用リードフレーム
JPH085563Y2 (ja) * 1990-03-31 1996-02-14 日本アビオニクス株式会社 高電力ハイブリッドic用金属パッケージ
JPH03290957A (ja) * 1990-04-06 1991-12-20 Sumitomo Special Metals Co Ltd プラスチックスパッケージ用リードフレーム材料
JPH03290956A (ja) * 1990-04-06 1991-12-20 Sumitomo Special Metals Co Ltd プラスチックスパッケージ用リードフレーム材料
DE69222084T2 (de) * 1991-05-17 1998-01-22 Fujitsu Ltd Oberflächenmontierbare Halbleiterpackung
US5831332A (en) * 1991-05-17 1998-11-03 Fujitsu Limited Semiconductor package for surface mounting
JPH0831559B2 (ja) * 1991-05-17 1996-03-27 富士通株式会社 半導体装置
KR0163871B1 (ko) * 1995-11-25 1998-12-01 김광호 하부에 히트 싱크가 부착된 솔더 볼 어레이 패키지
JP2008243522A (ja) * 2007-03-27 2008-10-09 Matsushita Electric Ind Co Ltd プラズマディスプレイパネル
JP6657947B2 (ja) * 2015-12-28 2020-03-04 Tdk株式会社 電子部品

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916353A (ja) * 1982-07-19 1984-01-27 Sumitomo Electric Ind Ltd リ−ドフレ−ム

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916353A (ja) * 1982-07-19 1984-01-27 Sumitomo Electric Ind Ltd リ−ドフレ−ム

Also Published As

Publication number Publication date
JPS60242653A (ja) 1985-12-02

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