JPH0580142B2 - - Google Patents

Info

Publication number
JPH0580142B2
JPH0580142B2 JP1265314A JP26531489A JPH0580142B2 JP H0580142 B2 JPH0580142 B2 JP H0580142B2 JP 1265314 A JP1265314 A JP 1265314A JP 26531489 A JP26531489 A JP 26531489A JP H0580142 B2 JPH0580142 B2 JP H0580142B2
Authority
JP
Japan
Prior art keywords
layer
polysilicon
emitter
region
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1265314A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0340432A (ja
Inventor
Richaado Gosu Jooji
Emesu Magudo Inguritsudo
Daa Marabia Shashii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH0340432A publication Critical patent/JPH0340432A/ja
Publication of JPH0580142B2 publication Critical patent/JPH0580142B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP1265314A 1980-07-08 1989-10-13 半導体装置 Granted JPH0340432A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/167,184 US4400865A (en) 1980-07-08 1980-07-08 Self-aligned metal process for integrated circuit metallization
US167184 2002-06-11

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP56099812A Division JPS5778136A (en) 1980-07-08 1981-06-29 Method of fabricating semiconductor device

Publications (2)

Publication Number Publication Date
JPH0340432A JPH0340432A (ja) 1991-02-21
JPH0580142B2 true JPH0580142B2 (enExample) 1993-11-08

Family

ID=22606300

Family Applications (3)

Application Number Title Priority Date Filing Date
JP56099812A Granted JPS5778136A (en) 1980-07-08 1981-06-29 Method of fabricating semiconductor device
JP1265314A Granted JPH0340432A (ja) 1980-07-08 1989-10-13 半導体装置
JP2330956A Granted JPH0418735A (ja) 1980-07-08 1990-11-30 バイポーラ型半導体装置の製造方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP56099812A Granted JPS5778136A (en) 1980-07-08 1981-06-29 Method of fabricating semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2330956A Granted JPH0418735A (ja) 1980-07-08 1990-11-30 バイポーラ型半導体装置の製造方法

Country Status (7)

Country Link
US (1) US4400865A (enExample)
EP (1) EP0043942B1 (enExample)
JP (3) JPS5778136A (enExample)
AU (1) AU7266181A (enExample)
BR (1) BR8104010A (enExample)
CA (1) CA1166760A (enExample)
DE (1) DE3177099D1 (enExample)

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US4758528A (en) * 1980-07-08 1988-07-19 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4471522A (en) * 1980-07-08 1984-09-18 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
DE3174824D1 (en) * 1980-12-17 1986-07-17 Matsushita Electric Industrial Co Ltd Semiconductor integrated circuit
US4508579A (en) * 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
US4521952A (en) * 1982-12-02 1985-06-11 International Business Machines Corporation Method of making integrated circuits using metal silicide contacts
US4551906A (en) * 1983-12-12 1985-11-12 International Business Machines Corporation Method for making self-aligned lateral bipolar transistors
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4636834A (en) * 1983-12-12 1987-01-13 International Business Machines Corporation Submicron FET structure and method of making
CA1260754A (en) * 1983-12-26 1989-09-26 Teiji Majima Method for forming patterns and apparatus used for carrying out the same
JPS6182482A (ja) * 1984-09-29 1986-04-26 Toshiba Corp ＧａＡｓ電界効果トランジスタの製造方法
EP0193934B1 (en) * 1985-03-07 1993-07-21 Kabushiki Kaisha Toshiba Semiconductor integreated circuit device and method of manufacturing the same
US5280188A (en) * 1985-03-07 1994-01-18 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and a plurality of MOS transistors
GB2172744B (en) * 1985-03-23 1989-07-19 Stc Plc Semiconductor devices
FR2579826B1 (fr) * 1985-03-26 1988-04-29 Radiotechnique Compelec Procede de realisation de contacts metalliques d'un transistor, et transistor ainsi obtenu
US4648173A (en) * 1985-05-28 1987-03-10 International Business Machines Corporation Fabrication of stud-defined integrated circuit structure
GB8528967D0 (en) * 1985-11-25 1986-01-02 Plessey Co Plc Semiconductor device manufacture
US4789560A (en) * 1986-01-08 1988-12-06 Advanced Micro Devices, Inc. Diffusion stop method for forming silicon oxide during the fabrication of IC devices
US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US4849344A (en) * 1986-12-11 1989-07-18 Fairchild Semiconductor Corporation Enhanced density modified isoplanar process
DE3751773T2 (de) * 1986-12-11 1996-11-28 Fairchild Semiconductor Modifiziertes isoplanares verfahren mit erhöhter dichte
IL82113A (en) * 1987-04-05 1992-08-18 Zvi Orbach Fabrication of customized integrated circuits
US4902533A (en) * 1987-06-19 1990-02-20 Motorola, Inc. Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide
JPS6415976A (en) * 1987-07-09 1989-01-19 Nec Corp Manufacture of semiconductor device
FR2618011B1 (fr) * 1987-07-10 1992-09-18 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire
JP2538269B2 (ja) * 1987-08-03 1996-09-25 富士通株式会社 半導体装置の製造方法
US5008208A (en) * 1988-12-07 1991-04-16 Honeywell Inc. Method of making planarized, self-aligned bipolar integrated circuits
JP2741393B2 (ja) * 1989-02-11 1998-04-15 猛英 白土 半導体装置
US5201993A (en) 1989-07-20 1993-04-13 Micron Technology, Inc. Anisotropic etch method
US5443998A (en) * 1989-08-01 1995-08-22 Cypress Semiconductor Corp. Method of forming a chlorinated silicon nitride barrier layer
GB2245418A (en) * 1990-06-20 1992-01-02 Koninkl Philips Electronics Nv A semiconductor device and a method of manufacturing such a device
US5229325A (en) * 1991-01-31 1993-07-20 Samsung Electronics Co., Ltd. Method for forming metal wirings of semiconductor device
KR930006128B1 (ko) * 1991-01-31 1993-07-07 삼성전자 주식회사 반도체장치의 금속 배선 형성방법
US5387813A (en) * 1992-09-25 1995-02-07 National Semiconductor Corporation Transistors with emitters having at least three sides
US5314841A (en) * 1993-04-30 1994-05-24 International Business Machines Corporation Method of forming a frontside contact to the silicon substrate of a SOI wafer
US5389553A (en) * 1993-06-30 1995-02-14 National Semiconductor Corporation Methods for fabrication of transistors
US5418175A (en) * 1994-05-06 1995-05-23 United Microelectronics Corporation Process for flat-cell mask ROM integrated circuit
US5950091A (en) * 1996-12-06 1999-09-07 Advanced Micro Devices, Inc. Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material
US6022815A (en) * 1996-12-31 2000-02-08 Intel Corporation Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique
JPH11102916A (ja) * 1997-09-29 1999-04-13 Nec Corp 半導体集積回路装置およびその設計方法
US6010934A (en) * 1998-03-02 2000-01-04 Texas Instruments - Acer Incorporated Method of making nanometer Si islands for single electron transistors
US6630520B1 (en) 1998-11-24 2003-10-07 Dow Global Technologies Inc. Composition containing a cross-linkable matrix precursor and a poragen, and a porous matrix prepared therefrom
US20060276043A1 (en) * 2003-03-21 2006-12-07 Johnson Mark A L Method and systems for single- or multi-period edge definition lithography
US7932613B2 (en) * 2009-03-27 2011-04-26 Globalfoundries Inc. Interconnect structure for a semiconductor device
CN105206568B (zh) * 2015-10-16 2018-06-05 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制备方法及其阵列基板

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US3184668A (en) * 1963-02-15 1965-05-18 Smith Kline French Lab Master-slave plural motor synchronizing system
JPS5339528B1 (enExample) * 1971-03-06 1978-10-21
US3750268A (en) * 1971-09-10 1973-08-07 Motorola Inc Poly-silicon electrodes for c-igfets
SE371894B (enExample) * 1973-04-16 1974-12-02 Sandberg S Sem
DE2403886A1 (de) * 1974-01-28 1975-08-07 Siemens Ag Schaltungsanordnung zum fortlaufenden aufbereiten von analog dargestellten fahrzeuggeschwindigkeitswerten zu digitalen mittelwerten
US3902926A (en) * 1974-02-21 1975-09-02 Signetics Corp Method of making an ion implanted resistor
US4038110A (en) * 1974-06-17 1977-07-26 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
US3984822A (en) * 1974-12-30 1976-10-05 Intel Corporation Double polycrystalline silicon gate memory device
DE2500061A1 (de) * 1975-01-02 1976-07-08 Dunlop Ag Einrichtung zur schlupfmessung
GB1527894A (en) * 1975-10-15 1978-10-11 Mullard Ltd Methods of manufacturing electronic devices
GB1535086A (en) * 1976-03-22 1978-12-06 Western Electric Co Manufacture of transistors
GB2003660A (en) 1977-08-19 1979-03-14 Plessey Co Ltd Deposition of material on a substrate
US4179222A (en) * 1978-01-11 1979-12-18 Systematix Controls, Inc. Flow turbulence generating and mixing device
US4173768A (en) * 1978-01-16 1979-11-06 Rca Corporation Contact for semiconductor devices
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4319395A (en) * 1979-06-28 1982-03-16 Motorola, Inc. Method of making self-aligned device
US4318751A (en) * 1980-03-13 1982-03-09 International Business Machines Corporation Self-aligned process for providing an improved high performance bipolar transistor
US4359816A (en) * 1980-07-08 1982-11-23 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits
US4322883A (en) * 1980-07-08 1982-04-06 International Business Machines Corporation Self-aligned metal process for integrated injection logic integrated circuits

Also Published As

Publication number Publication date
EP0043942A2 (en) 1982-01-20
JPH0322053B2 (enExample) 1991-03-26
JPS5778136A (en) 1982-05-15
JPH0570303B2 (enExample) 1993-10-04
EP0043942A3 (en) 1985-12-04
AU7266181A (en) 1982-01-14
JPH0418735A (ja) 1992-01-22
DE3177099D1 (en) 1989-10-05
EP0043942B1 (en) 1989-08-30
US4400865A (en) 1983-08-30
CA1166760A (en) 1984-05-01
BR8104010A (pt) 1982-03-16
JPH0340432A (ja) 1991-02-21

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