DE3177099D1 - Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions - Google Patents

Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions

Info

Publication number
DE3177099D1
DE3177099D1 DE8181104797T DE3177099T DE3177099D1 DE 3177099 D1 DE3177099 D1 DE 3177099D1 DE 8181104797 T DE8181104797 T DE 8181104797T DE 3177099 T DE3177099 T DE 3177099T DE 3177099 D1 DE3177099 D1 DE 3177099D1
Authority
DE
Germany
Prior art keywords
pattern
integrated circuits
dielectric regions
forming integrated
narrow dimensioned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181104797T
Other languages
English (en)
Inventor
George Richard Goth
Ingrid Emese Magdo
Shashi Dhar Malaviya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3177099D1 publication Critical patent/DE3177099D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
DE8181104797T 1980-07-08 1981-06-23 Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions Expired DE3177099D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/167,184 US4400865A (en) 1980-07-08 1980-07-08 Self-aligned metal process for integrated circuit metallization

Publications (1)

Publication Number Publication Date
DE3177099D1 true DE3177099D1 (en) 1989-10-05

Family

ID=22606300

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181104797T Expired DE3177099D1 (en) 1980-07-08 1981-06-23 Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions

Country Status (7)

Country Link
US (1) US4400865A (de)
EP (1) EP0043942B1 (de)
JP (3) JPS5778136A (de)
AU (1) AU7266181A (de)
BR (1) BR8104010A (de)
CA (1) CA1166760A (de)
DE (1) DE3177099D1 (de)

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CA1260754A (en) * 1983-12-26 1989-09-26 Teiji Majima Method for forming patterns and apparatus used for carrying out the same
JPS6182482A (ja) * 1984-09-29 1986-04-26 Toshiba Corp ＧａＡｓ電界効果トランジスタの製造方法
DE3688711T2 (de) * 1985-03-07 1993-12-16 Toshiba Kawasaki Kk Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung.
US5280188A (en) * 1985-03-07 1994-01-18 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and a plurality of MOS transistors
GB2172744B (en) * 1985-03-23 1989-07-19 Stc Plc Semiconductor devices
FR2579826B1 (fr) * 1985-03-26 1988-04-29 Radiotechnique Compelec Procede de realisation de contacts metalliques d'un transistor, et transistor ainsi obtenu
US4648173A (en) * 1985-05-28 1987-03-10 International Business Machines Corporation Fabrication of stud-defined integrated circuit structure
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US4789560A (en) * 1986-01-08 1988-12-06 Advanced Micro Devices, Inc. Diffusion stop method for forming silicon oxide during the fabrication of IC devices
US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
DE3751773T2 (de) * 1986-12-11 1996-11-28 Fairchild Semiconductor Modifiziertes isoplanares verfahren mit erhöhter dichte
US4849344A (en) * 1986-12-11 1989-07-18 Fairchild Semiconductor Corporation Enhanced density modified isoplanar process
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US4902533A (en) * 1987-06-19 1990-02-20 Motorola, Inc. Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide
JPS6415976A (en) * 1987-07-09 1989-01-19 Nec Corp Manufacture of semiconductor device
FR2618011B1 (fr) * 1987-07-10 1992-09-18 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire
JP2538269B2 (ja) * 1987-08-03 1996-09-25 富士通株式会社 半導体装置の製造方法
US5008208A (en) * 1988-12-07 1991-04-16 Honeywell Inc. Method of making planarized, self-aligned bipolar integrated circuits
JP2741393B2 (ja) * 1989-02-11 1998-04-15 猛英 白土 半導体装置
US5201993A (en) 1989-07-20 1993-04-13 Micron Technology, Inc. Anisotropic etch method
US5443998A (en) * 1989-08-01 1995-08-22 Cypress Semiconductor Corp. Method of forming a chlorinated silicon nitride barrier layer
GB2245418A (en) * 1990-06-20 1992-01-02 Koninkl Philips Electronics Nv A semiconductor device and a method of manufacturing such a device
KR930006128B1 (ko) * 1991-01-31 1993-07-07 삼성전자 주식회사 반도체장치의 금속 배선 형성방법
US5229325A (en) * 1991-01-31 1993-07-20 Samsung Electronics Co., Ltd. Method for forming metal wirings of semiconductor device
US5387813A (en) * 1992-09-25 1995-02-07 National Semiconductor Corporation Transistors with emitters having at least three sides
US5314841A (en) * 1993-04-30 1994-05-24 International Business Machines Corporation Method of forming a frontside contact to the silicon substrate of a SOI wafer
US5389553A (en) * 1993-06-30 1995-02-14 National Semiconductor Corporation Methods for fabrication of transistors
US5418175A (en) * 1994-05-06 1995-05-23 United Microelectronics Corporation Process for flat-cell mask ROM integrated circuit
US5950091A (en) * 1996-12-06 1999-09-07 Advanced Micro Devices, Inc. Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material
US6022815A (en) * 1996-12-31 2000-02-08 Intel Corporation Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique
JPH11102916A (ja) * 1997-09-29 1999-04-13 Nec Corp 半導体集積回路装置およびその設計方法
US6010934A (en) * 1998-03-02 2000-01-04 Texas Instruments - Acer Incorporated Method of making nanometer Si islands for single electron transistors
CN1325560C (zh) 1998-11-24 2007-07-11 陶氏环球技术公司 含可交联基质前体和致孔剂的组合物及由此组合物制成的多孔性基质
US20060276043A1 (en) * 2003-03-21 2006-12-07 Johnson Mark A L Method and systems for single- or multi-period edge definition lithography
US7932613B2 (en) * 2009-03-27 2011-04-26 Globalfoundries Inc. Interconnect structure for a semiconductor device
CN105206568B (zh) * 2015-10-16 2018-06-05 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制备方法及其阵列基板

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Also Published As

Publication number Publication date
AU7266181A (en) 1982-01-14
US4400865A (en) 1983-08-30
EP0043942A3 (en) 1985-12-04
CA1166760A (en) 1984-05-01
JPH0340432A (ja) 1991-02-21
JPH0580142B2 (de) 1993-11-08
JPH0570303B2 (de) 1993-10-04
EP0043942B1 (de) 1989-08-30
EP0043942A2 (de) 1982-01-20
JPH0322053B2 (de) 1991-03-26
JPS5778136A (en) 1982-05-15
JPH0418735A (ja) 1992-01-22
BR8104010A (pt) 1982-03-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee