GB2003660A - Deposition of material on a substrate - Google Patents

Deposition of material on a substrate

Info

Publication number
GB2003660A
GB2003660A GB7833641A GB7833641A GB2003660A GB 2003660 A GB2003660 A GB 2003660A GB 7833641 A GB7833641 A GB 7833641A GB 7833641 A GB7833641 A GB 7833641A GB 2003660 A GB2003660 A GB 2003660A
Authority
GB
United Kingdom
Prior art keywords
substrate
area
deposition
depositing
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB7833641A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB7833641A priority Critical patent/GB2003660A/en
Publication of GB2003660A publication Critical patent/GB2003660A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers

Abstract

A method of depositing an area 6, particularly of metal, on a substrate 1 includes the steps of defining a resist step 3 on the substrate, depositing a thickness of the material 5 to provide a uniform coverage of the step, unidirectionally etching the material to define the area 6 as an abutment to the step 3 and removing the resist 2 to leave the required area of material. <IMAGE>
GB7833641A 1977-08-19 1978-08-17 Deposition of material on a substrate Withdrawn GB2003660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB7833641A GB2003660A (en) 1977-08-19 1978-08-17 Deposition of material on a substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB3486577 1977-08-19
GB7833641A GB2003660A (en) 1977-08-19 1978-08-17 Deposition of material on a substrate

Publications (1)

Publication Number Publication Date
GB2003660A true GB2003660A (en) 1979-03-14

Family

ID=26262477

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7833641A Withdrawn GB2003660A (en) 1977-08-19 1978-08-17 Deposition of material on a substrate

Country Status (1)

Country Link
GB (1) GB2003660A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0010623A1 (en) * 1978-11-03 1980-05-14 International Business Machines Corporation Method for forming a laminated structure for highly integrated semiconductor devices with an insulating layer between two conductive layers
EP0081977A2 (en) * 1981-12-11 1983-06-22 Western Electric Company, Incorporated A maskless process for applying a patterned coating
US4400865A (en) 1980-07-08 1983-08-30 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4459320A (en) * 1981-12-11 1984-07-10 At&T Bell Laboratories Maskless process for applying a patterned solder mask coating
US4471522A (en) * 1980-07-08 1984-09-18 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
EP0240683A1 (en) * 1986-04-07 1987-10-14 International Business Machines Corporation Fabrication of insulated gallium arsenide-gate FET with self-aligned source/drain and submicron channel length
US4758528A (en) * 1980-07-08 1988-07-19 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
EP0313814A2 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Organic sidewall structures
EP0313815A2 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Formation of variable-width sidewall structures

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0010623A1 (en) * 1978-11-03 1980-05-14 International Business Machines Corporation Method for forming a laminated structure for highly integrated semiconductor devices with an insulating layer between two conductive layers
US4471522A (en) * 1980-07-08 1984-09-18 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4400865A (en) 1980-07-08 1983-08-30 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4758528A (en) * 1980-07-08 1988-07-19 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
WO1983002074A1 (en) * 1981-12-11 1983-06-23 Western Electric Co A maskless process for applying a patterned coating
EP0081977A3 (en) * 1981-12-11 1984-06-27 Western Electric Company, Incorporated A maskless process for applying a patterned coating
US4459320A (en) * 1981-12-11 1984-07-10 At&T Bell Laboratories Maskless process for applying a patterned solder mask coating
EP0081977A2 (en) * 1981-12-11 1983-06-22 Western Electric Company, Incorporated A maskless process for applying a patterned coating
EP0240683A1 (en) * 1986-04-07 1987-10-14 International Business Machines Corporation Fabrication of insulated gallium arsenide-gate FET with self-aligned source/drain and submicron channel length
EP0313814A2 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Organic sidewall structures
EP0313815A2 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Formation of variable-width sidewall structures
EP0313815A3 (en) * 1987-10-30 1990-11-22 International Business Machines Corporation Formation of variable-width sidewall structures
EP0313814A3 (en) * 1987-10-30 1991-01-02 International Business Machines Corporation Organic sidewall structures

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)