JPH0521338B2 - - Google Patents

Info

Publication number
JPH0521338B2
JPH0521338B2 JP60206180A JP20618085A JPH0521338B2 JP H0521338 B2 JPH0521338 B2 JP H0521338B2 JP 60206180 A JP60206180 A JP 60206180A JP 20618085 A JP20618085 A JP 20618085A JP H0521338 B2 JPH0521338 B2 JP H0521338B2
Authority
JP
Japan
Prior art keywords
layer
manufacturing
semiconductor
semiconductor device
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60206180A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6174370A (ja
Inventor
Aanorudasu Aperusu Yohanesu
Fuodefuridasu Rafuaeru Maasu Henrikasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of JPS6174370A publication Critical patent/JPS6174370A/ja
Publication of JPH0521338B2 publication Critical patent/JPH0521338B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H10P32/1414—
    • H10P32/171—
    • H10P76/4085—
    • H10W20/4451—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/103—Mask, dual function, e.g. diffusion and oxidation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching

Landscapes

  • Bipolar Transistors (AREA)
JP60206180A 1984-09-18 1985-09-18 半導体装置の製造方法 Granted JPS6174370A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8402856 1984-09-18
NL8402856A NL8402856A (nl) 1984-09-18 1984-09-18 Werkwijze voor het vervaardigen van een halfgeleiderinrichting.

Publications (2)

Publication Number Publication Date
JPS6174370A JPS6174370A (ja) 1986-04-16
JPH0521338B2 true JPH0521338B2 (cg-RX-API-DMAC10.html) 1993-03-24

Family

ID=19844483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60206180A Granted JPS6174370A (ja) 1984-09-18 1985-09-18 半導体装置の製造方法

Country Status (6)

Country Link
US (1) US4689872A (cg-RX-API-DMAC10.html)
EP (1) EP0180256B1 (cg-RX-API-DMAC10.html)
JP (1) JPS6174370A (cg-RX-API-DMAC10.html)
CA (1) CA1243131A (cg-RX-API-DMAC10.html)
DE (1) DE3574525D1 (cg-RX-API-DMAC10.html)
NL (1) NL8402856A (cg-RX-API-DMAC10.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7049624B2 (en) 2003-05-06 2006-05-23 Canon Kabushiki Kaisha Member and member manufacturing method

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722908A (en) * 1986-08-28 1988-02-02 Fairchild Semiconductor Corporation Fabrication of a bipolar transistor with a polysilicon ribbon
GB8621535D0 (en) * 1986-09-08 1986-10-15 British Telecomm Bipolar fabrication process
GB8621536D0 (en) * 1986-09-08 1986-10-15 British Telecomm Bipolar fabrication process
US5067002A (en) * 1987-01-30 1991-11-19 Motorola, Inc. Integrated circuit structures having polycrystalline electrode contacts
US4837176A (en) * 1987-01-30 1989-06-06 Motorola Inc. Integrated circuit structures having polycrystalline electrode contacts and process
GB2204992A (en) * 1987-05-05 1988-11-23 British Telecomm Bipolar transistor
US4772566A (en) * 1987-07-01 1988-09-20 Motorola Inc. Single tub transistor means and method
US5008207A (en) * 1989-09-11 1991-04-16 International Business Machines Corporation Method of fabricating a narrow base transistor
US5132765A (en) * 1989-09-11 1992-07-21 Blouse Jeffrey L Narrow base transistor and method of fabricating same
GB2236901A (en) * 1989-09-20 1991-04-17 Philips Nv A method of manufacturing a semiconductor device
NL9100062A (nl) * 1991-01-14 1992-08-03 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US5171705A (en) * 1991-11-22 1992-12-15 Supertex, Inc. Self-aligned structure and process for DMOS transistor
US5414283A (en) * 1993-11-19 1995-05-09 Ois Optical Imaging Systems, Inc. TFT with reduced parasitic capacitance
US6465865B1 (en) * 1996-01-05 2002-10-15 Micron Technology, Inc. Isolated structure and method of fabricating such a structure on a substrate
US6110798A (en) * 1996-01-05 2000-08-29 Micron Technology, Inc. Method of fabricating an isolation structure on a semiconductor substrate
US6656845B2 (en) * 2002-02-15 2003-12-02 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming semiconductor substrate with convex shaped active region
US6784076B2 (en) * 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3886569A (en) * 1970-01-22 1975-05-27 Ibm Simultaneous double diffusion into a semiconductor substrate
US4127931A (en) * 1974-10-04 1978-12-05 Nippon Electric Co., Ltd. Semiconductor device
US4074304A (en) * 1974-10-04 1978-02-14 Nippon Electric Company, Ltd. Semiconductor device having a miniature junction area and process for fabricating same
JPS5293278A (en) * 1976-01-30 1977-08-05 Matsushita Electronics Corp Manufacture for mos type semiconductor intergrated circuit
US4506437A (en) * 1978-05-26 1985-03-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4305760A (en) * 1978-12-22 1981-12-15 Ncr Corporation Polysilicon-to-substrate contact processing
US4285117A (en) * 1979-09-06 1981-08-25 Teletype Corporation Method of manufacturing a device in a silicon wafer
FR2508704B1 (fr) * 1981-06-26 1985-06-07 Thomson Csf Procede de fabrication de transistors bipolaires integres de tres petites dimensions
JPS5946105B2 (ja) * 1981-10-27 1984-11-10 日本電信電話株式会社 バイポ−ラ型トランジスタ装置及びその製法
NL8105920A (nl) * 1981-12-31 1983-07-18 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van een dergelijke halfgeleiderinrichting.
US4507171A (en) * 1982-08-06 1985-03-26 International Business Machines Corporation Method for contacting a narrow width PN junction region
US4545114A (en) * 1982-09-30 1985-10-08 Fujitsu Limited Method of producing semiconductor device
JPS5975661A (ja) * 1982-10-22 1984-04-28 Fujitsu Ltd 半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7049624B2 (en) 2003-05-06 2006-05-23 Canon Kabushiki Kaisha Member and member manufacturing method

Also Published As

Publication number Publication date
DE3574525D1 (de) 1990-01-04
EP0180256B1 (en) 1989-11-29
CA1243131A (en) 1988-10-11
EP0180256A1 (en) 1986-05-07
US4689872A (en) 1987-09-01
JPS6174370A (ja) 1986-04-16
NL8402856A (nl) 1986-04-16

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