JPH0519329B2 - - Google Patents
Info
- Publication number
- JPH0519329B2 JPH0519329B2 JP62139902A JP13990287A JPH0519329B2 JP H0519329 B2 JPH0519329 B2 JP H0519329B2 JP 62139902 A JP62139902 A JP 62139902A JP 13990287 A JP13990287 A JP 13990287A JP H0519329 B2 JPH0519329 B2 JP H0519329B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- signal
- setting data
- controlled oscillator
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
- H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62139902A JPS63304721A (ja) | 1987-06-05 | 1987-06-05 | 信号発生装置 |
| US07/200,700 US4849714A (en) | 1987-06-05 | 1988-05-31 | Signal generating apparatus |
| EP88108930A EP0295515A1 (en) | 1987-06-05 | 1988-06-03 | Signal generating apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62139902A JPS63304721A (ja) | 1987-06-05 | 1987-06-05 | 信号発生装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63304721A JPS63304721A (ja) | 1988-12-13 |
| JPH0519329B2 true JPH0519329B2 (enExample) | 1993-03-16 |
Family
ID=15256284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62139902A Granted JPS63304721A (ja) | 1987-06-05 | 1987-06-05 | 信号発生装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4849714A (enExample) |
| EP (1) | EP0295515A1 (enExample) |
| JP (1) | JPS63304721A (enExample) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940011436B1 (ko) * | 1989-04-19 | 1994-12-15 | 가부시끼가이샤 히다찌세이사꾸쇼 | 자기디스크 기억장치 |
| JPH07101865B2 (ja) * | 1989-06-23 | 1995-11-01 | 日本電気株式会社 | 無線送信装置の周波数設定方式 |
| DE4228834A1 (de) * | 1992-08-29 | 1994-03-03 | Thomson Brandt Gmbh | Verfahren und Vorrichtung zum Abgleich einer PLL Stufe |
| US5940608A (en) | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
| US6912680B1 (en) | 1997-02-11 | 2005-06-28 | Micron Technology, Inc. | Memory system with dynamic timing correction |
| US5946244A (en) | 1997-03-05 | 1999-08-31 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
| US6173432B1 (en) | 1997-06-20 | 2001-01-09 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
| US5940609A (en) * | 1997-08-29 | 1999-08-17 | Micorn Technology, Inc. | Synchronous clock generator including a false lock detector |
| US6269451B1 (en) | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
| US6338127B1 (en) | 1998-08-28 | 2002-01-08 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same |
| US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
| US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
| US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
| US6470060B1 (en) | 1999-03-01 | 2002-10-22 | Micron Technology, Inc. | Method and apparatus for generating a phase dependent control signal |
| KR100725935B1 (ko) * | 2001-03-23 | 2007-06-11 | 삼성전자주식회사 | 프랙셔널-앤 주파수 합성기용 위상 고정 루프 회로 |
| US6801989B2 (en) | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
| US7168027B2 (en) | 2003-06-12 | 2007-01-23 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
| US7234070B2 (en) | 2003-10-27 | 2007-06-19 | Micron Technology, Inc. | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4272729A (en) * | 1979-05-10 | 1981-06-09 | Harris Corporation | Automatic pretuning of a voltage controlled oscillator in a frequency synthesizer using successive approximation |
| US4330758A (en) * | 1980-02-20 | 1982-05-18 | Motorola, Inc. | Synchronized frequency synthesizer with high speed lock |
| FR2514968A1 (fr) * | 1981-10-16 | 1983-04-22 | Trt Telecom Radio Electr | Synthetiseur de frequence a accord rapide |
| JPS62146020A (ja) * | 1985-12-20 | 1987-06-30 | Yokogawa Medical Syst Ltd | Pll周波数シンセサイザ |
| US4714899A (en) * | 1986-09-30 | 1987-12-22 | Motorola, Inc. | Frequency synthesizer |
-
1987
- 1987-06-05 JP JP62139902A patent/JPS63304721A/ja active Granted
-
1988
- 1988-05-31 US US07/200,700 patent/US4849714A/en not_active Expired - Fee Related
- 1988-06-03 EP EP88108930A patent/EP0295515A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0295515A1 (en) | 1988-12-21 |
| US4849714A (en) | 1989-07-18 |
| JPS63304721A (ja) | 1988-12-13 |
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