JPH0517708B2 - - Google Patents

Info

Publication number
JPH0517708B2
JPH0517708B2 JP60153406A JP15340685A JPH0517708B2 JP H0517708 B2 JPH0517708 B2 JP H0517708B2 JP 60153406 A JP60153406 A JP 60153406A JP 15340685 A JP15340685 A JP 15340685A JP H0517708 B2 JPH0517708 B2 JP H0517708B2
Authority
JP
Japan
Prior art keywords
chip
metal
etching
contact pad
support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60153406A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6149443A (ja
Inventor
Gerudamansu Piitaa
Suwami Masado Gangadaara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS6149443A publication Critical patent/JPS6149443A/ja
Publication of JPH0517708B2 publication Critical patent/JPH0517708B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W70/635—
    • H10W70/095—
    • H10W70/611—
    • H10W90/401—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H10W72/07251—
    • H10W72/20—
    • H10W90/724—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP60153406A 1984-08-13 1985-07-13 チツプ介在体の製造方法 Granted JPS6149443A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US639988 1984-08-13
US06/639,988 US4617730A (en) 1984-08-13 1984-08-13 Method of fabricating a chip interposer

Publications (2)

Publication Number Publication Date
JPS6149443A JPS6149443A (ja) 1986-03-11
JPH0517708B2 true JPH0517708B2 (enExample) 1993-03-09

Family

ID=24566380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60153406A Granted JPS6149443A (ja) 1984-08-13 1985-07-13 チツプ介在体の製造方法

Country Status (4)

Country Link
US (1) US4617730A (enExample)
EP (1) EP0171662B1 (enExample)
JP (1) JPS6149443A (enExample)
DE (1) DE3578614D1 (enExample)

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US4924589A (en) * 1988-05-16 1990-05-15 Leedy Glenn J Method of making and testing an integrated circuit
US6288561B1 (en) * 1988-05-16 2001-09-11 Elm Technology Corporation Method and apparatus for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus
US5020219A (en) * 1988-05-16 1991-06-04 Leedy Glenn J Method of making a flexible tester surface for testing integrated circuits
US5225771A (en) * 1988-05-16 1993-07-06 Dri Technology Corp. Making and testing an integrated circuit using high density probe points
US5512397A (en) * 1988-05-16 1996-04-30 Leedy; Glenn J. Stepper scanner discretionary lithography and common mask discretionary lithography for integrated circuits
DE68925894T2 (de) * 1988-09-15 1996-10-31 Pacific Trinetics Corp Verfahren zum herstellen von öffnungen in keramischen integrierten schaltungspackungen
CA2002213C (en) * 1988-11-10 1999-03-30 Iwona Turlik High performance integrated circuit chip package and method of making same
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JP2765673B2 (ja) * 1992-06-04 1998-06-18 インターナショナル・ビジネス・マシーンズ・コーポレイション メタライゼーション層及びその形成方法
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JPH0945805A (ja) * 1995-07-31 1997-02-14 Fujitsu Ltd 配線基板、半導体装置及び半導体装置を配線基板から取り外す方法並びに半導体装置の製造方法
US6405431B1 (en) 1996-06-27 2002-06-18 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing build-up multi-layer printed circuit board by using yag laser
US6720500B1 (en) * 1996-07-22 2004-04-13 Honda Giken Kogyo Kabushiki Kaisha Plug-in type electronic control unit, structure of connection of wiring board with plug member, unit of connection of electronic part with wiring board, and process for mounting electronic part
DE19632200C2 (de) * 1996-08-09 2002-09-05 Bosch Gmbh Robert Multichipmodul
JP4234205B2 (ja) * 1996-11-08 2009-03-04 ダブリュ．エル．ゴア アンド アソシエイツ，インコーポレイティド 電子アセンブリおよび電子物品内でのヴァイアのインダクタンスを低減する方法
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US5973391A (en) * 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
US6833613B1 (en) * 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts
JPH11187542A (ja) * 1997-12-18 1999-07-09 Furukawa Electric Co Ltd:The バスバー配線板の製造方法
US6620731B1 (en) * 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6023029A (en) * 1998-03-19 2000-02-08 International Business Machines Corporation Use of blind vias for soldered interconnections between substrates and printed wiring boards
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US6627998B1 (en) * 2000-07-27 2003-09-30 International Business Machines Corporation Wafer scale thin film package
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KR102720747B1 (ko) * 2015-03-12 2024-10-23 소니그룹주식회사 촬상 장치, 제조 방법 및 전자 기기
US10468363B2 (en) 2015-08-10 2019-11-05 X-Celeprint Limited Chiplets with connection posts

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Also Published As

Publication number Publication date
EP0171662A2 (en) 1986-02-19
DE3578614D1 (de) 1990-08-16
EP0171662A3 (en) 1987-01-14
US4617730A (en) 1986-10-21
EP0171662B1 (en) 1990-07-11
JPS6149443A (ja) 1986-03-11

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