JPH0226392B2 - - Google Patents

Info

Publication number
JPH0226392B2
JPH0226392B2 JP58085184A JP8518483A JPH0226392B2 JP H0226392 B2 JPH0226392 B2 JP H0226392B2 JP 58085184 A JP58085184 A JP 58085184A JP 8518483 A JP8518483 A JP 8518483A JP H0226392 B2 JPH0226392 B2 JP H0226392B2
Authority
JP
Japan
Prior art keywords
layer
route
mask
interconnect
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58085184A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5928366A (ja
Inventor
Maachin Shaiburu Hooru
Shuaberudo Jon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5928366A publication Critical patent/JPS5928366A/ja
Publication of JPH0226392B2 publication Critical patent/JPH0226392B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H10W70/095—
    • H10W70/611—
    • H10W70/685—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H10W90/724—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP58085184A 1982-07-22 1983-05-17 電気的相互接続パツケ−ジを製造する方法 Granted JPS5928366A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/400,800 US4430365A (en) 1982-07-22 1982-07-22 Method for forming conductive lines and vias
US400800 1995-03-07

Publications (2)

Publication Number Publication Date
JPS5928366A JPS5928366A (ja) 1984-02-15
JPH0226392B2 true JPH0226392B2 (enExample) 1990-06-08

Family

ID=23585071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58085184A Granted JPS5928366A (ja) 1982-07-22 1983-05-17 電気的相互接続パツケ−ジを製造する方法

Country Status (4)

Country Link
US (1) US4430365A (enExample)
EP (1) EP0099544B1 (enExample)
JP (1) JPS5928366A (enExample)
DE (1) DE3366774D1 (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536470A (en) * 1982-09-07 1985-08-20 International Business Machines Corporation Method and apparatus for making a mask conforming to a ceramic substrate metallization pattern
US4526859A (en) * 1983-12-12 1985-07-02 International Business Machines Corporation Metallization of a ceramic substrate
US4552615A (en) * 1984-05-21 1985-11-12 International Business Machines Corporation Process for forming a high density metallurgy system on a substrate and structure thereof
JPS6112054A (ja) * 1984-06-22 1986-01-20 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 半導体パツケ−ジ製造方法
JPS6156493A (ja) * 1984-08-28 1986-03-22 日本電気株式会社 多層回路基板の電源配線構造
US4621045A (en) * 1985-06-03 1986-11-04 Motorola, Inc. Pillar via process
US4814855A (en) * 1986-04-29 1989-03-21 International Business Machines Corporation Balltape structure for tape automated bonding, multilayer packaging, universal chip interconnection and energy beam processes for manufacturing balltape
US4721689A (en) * 1986-08-28 1988-01-26 International Business Machines Corporation Method for simultaneously forming an interconnection level and via studs
GB2199183B (en) * 1986-12-23 1990-07-04 Gen Electric Plc Interconnection formation in multilayer circuits
US4922325A (en) * 1987-10-02 1990-05-01 American Telephone And Telegraph Company Multilayer ceramic package with high frequency connections
US4982266A (en) * 1987-12-23 1991-01-01 Texas Instruments Incorporated Integrated circuit with metal interconnecting layers above and below active circuitry
US4880684A (en) * 1988-03-11 1989-11-14 International Business Machines Corporation Sealing and stress relief layers and use thereof
JPH02148862A (ja) * 1988-11-30 1990-06-07 Hitachi Ltd 回路素子パッケージ、キャリヤ基板および製造方法
US4980034A (en) * 1989-04-04 1990-12-25 Massachusetts Institute Of Technology High-density, multi-level interconnects, flex circuits, and tape for TAB
US5106461A (en) * 1989-04-04 1992-04-21 Massachusetts Institute Of Technology High-density, multi-level interconnects, flex circuits, and tape for tab
USRE34291E (en) * 1989-09-27 1993-06-22 Gec-Marconi Electronic Systems Corp. Hybrid module electronics package
US4996630A (en) * 1989-09-27 1991-02-26 Plessey Electronic Systems Corp. Hybrid module electronics package
JP2773366B2 (ja) * 1990-03-19 1998-07-09 富士通株式会社 多層配線基板の形成方法
US5219669A (en) * 1990-04-26 1993-06-15 International Business Machines Corporation Layer thin film wiring process featuring self-alignment of vias
US5130229A (en) * 1990-04-26 1992-07-14 International Business Machines Corporation Multi layer thin film wiring process featuring self-alignment of vias
DE69023765T2 (de) * 1990-07-31 1996-06-20 Ibm Verfahren zur Herstellung von Bauelementen mit übereinander angeordneten Feldeffekttransistoren mit Wolfram-Gitter und sich daraus ergebende Struktur.
US5302219A (en) * 1991-04-03 1994-04-12 Coors Electronic Package Company Method for obtaining via patterns in ceramic sheets
US5292624A (en) * 1992-09-14 1994-03-08 International Technology Research Institute Method for forming a metallurgical interconnection layer package for a multilayer ceramic substrate
US5378927A (en) * 1993-05-24 1995-01-03 International Business Machines Corporation Thin-film wiring layout for a non-planar thin-film structure
US5712192A (en) * 1994-04-26 1998-01-27 International Business Machines Corporation Process for connecting an electrical device to a circuit substrate
US6429113B1 (en) 1994-04-26 2002-08-06 International Business Machines Corporation Method for connecting an electrical device to a circuit substrate
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
JP3160198B2 (ja) * 1995-02-08 2001-04-23 インターナショナル・ビジネス・マシーンズ・コーポレ−ション デカップリング・コンデンサが形成された半導体基板及びこれの製造方法
US5671116A (en) * 1995-03-10 1997-09-23 Lam Research Corporation Multilayered electrostatic chuck and method of manufacture thereof
US6191484B1 (en) * 1995-07-28 2001-02-20 Stmicroelectronics, Inc. Method of forming planarized multilevel metallization in an integrated circuit
US6260264B1 (en) 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
KR100875625B1 (ko) * 2005-11-14 2008-12-24 티디케이가부시기가이샤 복합 배선 기판 및 그 제조 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3605260A (en) 1968-11-12 1971-09-20 Gen Motors Corp Method of making multilayer printed circuits
US3726002A (en) 1971-08-27 1973-04-10 Ibm Process for forming a multi-layer glass-metal module adaptable for integral mounting to a dissimilar refractory substrate
US3853715A (en) 1973-12-20 1974-12-10 Ibm Elimination of undercut in an anodically active metal during chemical etching
US4040891A (en) 1976-06-30 1977-08-09 Ibm Corporation Etching process utilizing the same positive photoresist layer for two etching steps
US4045302A (en) 1976-07-08 1977-08-30 Burroughs Corporation Multilevel metallization process
US4172004A (en) 1977-10-20 1979-10-23 International Business Machines Corporation Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
US4132586A (en) 1977-12-20 1979-01-02 International Business Machines Corporation Selective dry etching of substrates
US4184909A (en) 1978-08-21 1980-01-22 International Business Machines Corporation Method of forming thin film interconnection systems
US4272561A (en) 1979-05-29 1981-06-09 International Business Machines Corporation Hybrid process for SBD metallurgies

Also Published As

Publication number Publication date
US4430365A (en) 1984-02-07
JPS5928366A (ja) 1984-02-15
DE3366774D1 (en) 1986-11-13
EP0099544A1 (en) 1984-02-01
EP0099544B1 (en) 1986-10-08

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