JPH0448627U - - Google Patents
Info
- Publication number
- JPH0448627U JPH0448627U JP1990067043U JP6704390U JPH0448627U JP H0448627 U JPH0448627 U JP H0448627U JP 1990067043 U JP1990067043 U JP 1990067043U JP 6704390 U JP6704390 U JP 6704390U JP H0448627 U JPH0448627 U JP H0448627U
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- electrode structure
- semiconductor device
- film material
- mutual diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 4
- 238000009792 diffusion process Methods 0.000 claims 2
- 229910008484 TiSi Inorganic materials 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 239000007769 metal material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05562—On the entire exposed surface of the internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2224/05687—Ceramics, e.g. crystalline carbides, nitrides or oxides
Description
第1図は本考案の一実施例を示すパツド電極構
造の構成図、第2図はパツド電極と一体の配線に
実施した場合の構成図、第3図は本考案の他の実
施例を示すバンプ電極構造の構成図、第4図は従
来のバンプ電極構造の構成図である。 1,11……Si基板、2,12……酸化膜、
3……A1膜、13……A1パツド、14……接
着層、15……バリヤメタル、5……Cu膜、6
……酸化防止用薄膜、13……A1パツド、16
……Cuバンプ、17……酸化防止用薄膜。
造の構成図、第2図はパツド電極と一体の配線に
実施した場合の構成図、第3図は本考案の他の実
施例を示すバンプ電極構造の構成図、第4図は従
来のバンプ電極構造の構成図である。 1,11……Si基板、2,12……酸化膜、
3……A1膜、13……A1パツド、14……接
着層、15……バリヤメタル、5……Cu膜、6
……酸化防止用薄膜、13……A1パツド、16
……Cuバンプ、17……酸化防止用薄膜。
Claims (1)
- 【実用新案登録請求の範囲】 (1) Cu薄膜を用いた電極構造において、前記
Cu薄膜上に耐酸化性、極薄膜性およびCuとの
相互耐拡散性を備えた薄膜材が形成されているこ
とを特徴とする半導体装置の電極構造。 (2) Cuを用いたバンプ電極構造において、前
記Cu表面に耐酸化性、極薄膜性およびCuとの
相互耐拡散性を備えた薄膜材が形成されているこ
とを特徴とする半導体装置の電極構造。 (3) 前記薄膜材が高融点金属材で形成されてい
る第1請求項または第2請求項記載の半導体装置
の電極構造。 (4) 前記薄膜材がA12O3,TiN、または
TiSi2,WSi2の化合物で形成されている
第1請求項または第2請求項記載の半導体装置の
電極構造。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990067043U JPH0448627U (ja) | 1990-06-01 | 1990-06-25 | |
US07/914,049 US5272376A (en) | 1990-06-01 | 1992-07-14 | Electrode structure for a semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5819990 | 1990-06-01 | ||
JP1990067043U JPH0448627U (ja) | 1990-06-01 | 1990-06-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0448627U true JPH0448627U (ja) | 1992-04-24 |
Family
ID=31948589
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1990067043U Pending JPH0448627U (ja) | 1990-06-01 | 1990-06-25 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0448627U (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878410A (ja) * | 1994-09-05 | 1996-03-22 | Mitsubishi Electric Corp | 配線接続部及びその製造方法 |
JP2003503852A (ja) * | 1999-06-28 | 2003-01-28 | ユナキス・バルツェルス・アクチェンゲゼルシャフト | 構造部材およびその製造方法 |
WO2018015156A1 (en) * | 2016-07-19 | 2018-01-25 | Danfoss Silicon Power Gmbh | Electrical assembly comprising a metal body arranged on a semiconductor chip and a connecting material arranged between the semiconductor chip and the metal body and connecting them |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6020522A (ja) * | 1983-07-15 | 1985-02-01 | Hitachi Ltd | 半導体装置 |
JPS62145758A (ja) * | 1985-12-16 | 1987-06-29 | ナシヨナル・セミコンダクタ−・コ−ポレ−シヨン | パラジウムを用いる銅製ボンデイングパツドの酸化防止法 |
-
1990
- 1990-06-25 JP JP1990067043U patent/JPH0448627U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6020522A (ja) * | 1983-07-15 | 1985-02-01 | Hitachi Ltd | 半導体装置 |
JPS62145758A (ja) * | 1985-12-16 | 1987-06-29 | ナシヨナル・セミコンダクタ−・コ−ポレ−シヨン | パラジウムを用いる銅製ボンデイングパツドの酸化防止法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0878410A (ja) * | 1994-09-05 | 1996-03-22 | Mitsubishi Electric Corp | 配線接続部及びその製造方法 |
JP2003503852A (ja) * | 1999-06-28 | 2003-01-28 | ユナキス・バルツェルス・アクチェンゲゼルシャフト | 構造部材およびその製造方法 |
WO2018015156A1 (en) * | 2016-07-19 | 2018-01-25 | Danfoss Silicon Power Gmbh | Electrical assembly comprising a metal body arranged on a semiconductor chip and a connecting material arranged between the semiconductor chip and the metal body and connecting them |
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