JPS61170056A - 半導体装置の電極材料 - Google Patents

半導体装置の電極材料

Info

Publication number
JPS61170056A
JPS61170056A JP60011353A JP1135385A JPS61170056A JP S61170056 A JPS61170056 A JP S61170056A JP 60011353 A JP60011353 A JP 60011353A JP 1135385 A JP1135385 A JP 1135385A JP S61170056 A JPS61170056 A JP S61170056A
Authority
JP
Japan
Prior art keywords
semiconductor device
film
copper
electrode
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60011353A
Other languages
English (en)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP60011353A priority Critical patent/JPS61170056A/ja
Publication of JPS61170056A publication Critical patent/JPS61170056A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に於ける電極材料構成に関する。
〔従来の技術〕
従来、半導体装置に於けるパッド部電極材料構成は、第
１図及び第２図に示す如き構成を用いるのが通例であっ
た。すなわち、第１図に於いてシリコン基板１の表面に
はシリコン酸化膜２が形成士＋−Ｉ　けＸｉ　Ｉ＋１・
ｌ酩ｌし日ＨすＬ−だＥＴ１÷ム柄へ１ソ澹にト穴を通
して拡散層Ｓが形成され、前記シリコン酸化膜２上には
第１の電極配線４がシリコン又はシリサイド等で形成さ
れ、層間絶縁膜５を介してアルミニウム配線６が施され
、表面保護膜７が形成され、該表面保護膜７にはパッド
部穴開けが成され、パッド部８が形成され、該パッド部
８の電極表面はアルミニウムで形成されて成る。
第２図は、従来技術に於けるパッド電極材料構成の他の
例であり、シリコン基板１１．シリコン酸化膜１２．拡
散層１５．第１の電極配線１４゜層間絶縁膜１．５．ア
ルミニウム配線１６１表面保護膜１７等は第１図の例と
同様な構成であり、パッド部にクロム膜１８と金膜１９
から成る電極が形成されて成る。
〔発明が解決しようとする問題点〕
しかし上記従来技術では次の如き問題点が有った。すな
わち、 （１）　　アル４＝ウム配線の微細化に伴う信頼度の低
下、 （２）　　全翼極材料使用によるコスト高、等である。
〔問題点を解決するための手段〕゛ 前記問題点を解決するために以下の如き手段を講じる。
すなわち、半導体装置の電極材料に関し、半導体装置の
少くとも外部電極との接続の為のパッド電極表面は、銅
又は銅合金膜で形成されて成る事を特徴とする。
〔作用〕
前記の如く、パッド電極部表面を銅又は銅合金膜と成す
事により、パッド部でのアルミニウム線又は金線との接
続性能を損う事なく、且つ信頼度の向上やコストダウン
を図る事が出来る作用が有る。
〔実施例〕
以下、実施例により本発明を詳述する。
第３図は本発明の一実施例を示す半導体装置の要部の断
面図である。すなわち、シリコン基板２１の表面にはシ
リコン酸化膜２２が形成され、該シリコン酸化膜２２に
開けられたコンタクト穴を通して拡散層２５が形成され
、前記シリコン酸化膜２２上には＃！１の電極部、１１
２４がシリコン又はシリサイド等で形成され、眉間絶縁
膜２５を介して銅配線２６が施され、表面保護膜２７が
形成され、該表面保護膜２７にはパッド部穴開けが成さ
れ１パッド部２Ｂが形成され、該パッド部２日の電極表
面は銅で形成されて成る。
第４図は本発明の他の実施例であり、シリコン基板３１
．シリコン酸化膜３２．拡散層３３．第１の電極配線ｓ
４１層間絶縁膜３５．アルミニウム配線５６１表面保護
膜３７が形成され、パッド部に銅膜３Ｂから成る電極が
形成されて成る。
尚、銅膜２８，３８はＯｕ、Ｎｉ、０ｕ−Ａｌ。
Ｏｕ　−Ｚ　ｎ等の銅合金でありても良く、更にＮ１膜
とＯｕ膜等の如く多層膜構造であっても良い。
更に銅あるいは銅合金膜による電極配線が半導体装置の
内部配線等に用いられても同等の効果を有する事は云う
までも無い。
〔発明の効果〕
本発明の如く銅あるいは銅合金膜を半導体装置の電極配
線として用いる事により、高信頼度で且つ低コストの半
導体装置が製作できる効果がある
【図面の簡単な説明】
第１図及び第２図は従来技術の例を示す半導体装置の要
部の断面図、第３図及び第４図は本発明の実施例を示す
半導体装置の要部の断面図である１、１１．２１．３１
・・・・・・シリコン基板２．１２，２２．３２・・・
・・・シリコン酸化膜Ｓ、１５，２５．５５・・・・・
・拡散層４．１４，２４．３４・・・・・・第１の電極
配線５．１５，２５．５５・・・・・・層間絶縁膜６．
１６．５６・・・・・・・・・・・・・・・アルミニウ
ム電極配線 ７．１７，２７．３７・・・・・・表面保護膜８．２５
・・・・・・パッド部

Claims (1)

    【特許請求の範囲】
  1. 半導体装置の少くとも外部電極との接続の為のパッド電
    極部表面は、銅又は銅合金膜で形成されて成る事を特徴
    とする半導体装置の電極材料。
JP60011353A 1985-01-24 1985-01-24 半導体装置の電極材料 Pending JPS61170056A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60011353A JPS61170056A (ja) 1985-01-24 1985-01-24 半導体装置の電極材料

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60011353A JPS61170056A (ja) 1985-01-24 1985-01-24 半導体装置の電極材料

Publications (1)

Publication Number Publication Date
JPS61170056A true JPS61170056A (ja) 1986-07-31

Family

ID=11775667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60011353A Pending JPS61170056A (ja) 1985-01-24 1985-01-24 半導体装置の電極材料

Country Status (1)

Country Link
JP (1) JPS61170056A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4853188A (en) * 1985-11-14 1989-08-01 Kabushiki Kaisha Tiyoda Seisakusho Cell for placing solid matters on a slide glass under centrifugal force
EP0588577A3 (en) * 1992-09-14 1994-04-20 Dow Corning Corporation Hermetically sealed integrated circuits
US5719448A (en) * 1989-03-07 1998-02-17 Seiko Epson Corporation Bonding pad structures for semiconductor integrated circuits
US9829418B2 (en) 2013-04-09 2017-11-28 Sakura Seiki Co., Ltd. Centrifugal smearing device and sealed rotating container

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4853188A (en) * 1985-11-14 1989-08-01 Kabushiki Kaisha Tiyoda Seisakusho Cell for placing solid matters on a slide glass under centrifugal force
US5719448A (en) * 1989-03-07 1998-02-17 Seiko Epson Corporation Bonding pad structures for semiconductor integrated circuits
EP0588577A3 (en) * 1992-09-14 1994-04-20 Dow Corning Corporation Hermetically sealed integrated circuits
US9829418B2 (en) 2013-04-09 2017-11-28 Sakura Seiki Co., Ltd. Centrifugal smearing device and sealed rotating container

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