JPH01214138A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH01214138A
JPH01214138A JP4115688A JP4115688A JPH01214138A JP H01214138 A JPH01214138 A JP H01214138A JP 4115688 A JP4115688 A JP 4115688A JP 4115688 A JP4115688 A JP 4115688A JP H01214138 A JPH01214138 A JP H01214138A
Authority
JP
Japan
Prior art keywords
layer
aluminum
wiring
pure
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4115688A
Other languages
English (en)
Inventor
Makoto Ito
誠 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4115688A priority Critical patent/JPH01214138A/ja
Publication of JPH01214138A publication Critical patent/JPH01214138A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は特性上アルミ合金を配線及びボンディングパッ
ドとして使用する半導体装置に関し、特に配線およびボ
ンディングパッドの耐食性の改善に関する。
〔従来の技術〕
従来、アルミ合金を配線材料として使用する場合ボンデ
ィングパッド配線の表面は、構成元素であるアルミニウ
ムと、添加元素、シリコンもしくは銅などの合金となっ
ていた。
〔発明が解決しようとする問題点〕
ＬＳＩの配線材料はアルミニウムに少量の添加元素を加
えたアルミ合金が広く使用されている。
特に高集積された微細ＬＳＩではアルミニウムーシリコ
ン合金や、アルミニウムー銅−シリコン合金の使用は浅
いＰｎ接合へのオーミックコンタクトを形成し、耐マイ
グレーシヨン耐量の改善のため必要となっているが、一
方で、アルミ合金は純アルミニウムと比べ均一な酸化保
護膜を生成せず、また合金元素間でイオン化傾向の異な
る為ガルバニック腐食を生じやすく耐食性が純アルミニ
ウムより悪いという欠点がある。
〔問題点を解決するための手段〕
本発明の半導体装置の配線およびボンディングパッドは
下地にアルミニウムと小量、添加元素として銅やシリコ
ンを含むアルミ合金層と、そのアルミ合金層の上層に純
アルミニウム層を有している。
〔実施例〕
次に本発明について図面を参照して説明する。
第１図は本発明の一実施例でボンディングパッド部分の
縦断面図である。第１図において、酸化膜１を下地とし
て、スパッタ法などによりアルミ合金層２を付ける。連
続して純アルミニウム層３を形成し保護膜４を形成して
ボンディングパッドを形成する。
第２図は本発明の実施例２の縦断面図である。
７ノペ合金層２と、純アルミニウム層３の中間に高融点
金属薄膜タングステン膜５を、熱拡散防止用のバリアと
して使用している。
〔発明の効果〕
以上説明したように本発明はアルミ配線やアルミボンデ
ィングパッドの表面を純アルミニウム層で被覆し、化学
的な活性なアルミ合金層を下層とする多層構造を採用す
ることにより化学的に安定で腐食に強いアルミ配線やア
ルミポンデイソゲバッドを得られる効果がある。
【図面の簡単な説明】
第１図は本発明の一実施例のボンディングパッド部分の
縦断面図である。 １・・・・・・酸化膜、２・・・・・・純アルミニウム
層、３・・・・・・アルミ合金層、４・・・・・・保護
膜、第２図は本発明の実施例２のボンディングパッド部
分の縦断面図である。 １・・・・・・酸化膜、２・・・・・・純アルミニウム
層、３・・・・・・アルミ合金層、４・・・・・・保護
膜、５・・・・・・高融点金属層。 代理人　弁理士　　内　原　　　音

Claims (1)

    【特許請求の範囲】
  1. 　アルミ合金層を下層として純アルミ層を上層とする多
    層構造のボンディングパッドと配線を有することを特徴
    とする半導体装置。
JP4115688A 1988-02-23 1988-02-23 半導体装置 Pending JPH01214138A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4115688A JPH01214138A (ja) 1988-02-23 1988-02-23 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4115688A JPH01214138A (ja) 1988-02-23 1988-02-23 半導体装置

Publications (1)

Publication Number Publication Date
JPH01214138A true JPH01214138A (ja) 1989-08-28

Family

ID=12600558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4115688A Pending JPH01214138A (ja) 1988-02-23 1988-02-23 半導体装置

Country Status (1)

Country Link
JP (1) JPH01214138A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08220382A (ja) * 1995-02-14 1996-08-30 Nec Corp ２次元光ファイバアレイ及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08220382A (ja) * 1995-02-14 1996-08-30 Nec Corp ２次元光ファイバアレイ及びその製造方法

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