JPS5892733U - 半導体装置の電極構造 - Google Patents

半導体装置の電極構造

Info

Publication number
JPS5892733U
JPS5892733U JP1981186609U JP18660981U JPS5892733U JP S5892733 U JPS5892733 U JP S5892733U JP 1981186609 U JP1981186609 U JP 1981186609U JP 18660981 U JP18660981 U JP 18660981U JP S5892733 U JPS5892733 U JP S5892733U
Authority
JP
Japan
Prior art keywords
electrode pattern
electrode structure
semiconductor devices
protective film
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981186609U
Other languages
English (en)
Inventor
誠 田中
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP1981186609U priority Critical patent/JPS5892733U/ja
Publication of JPS5892733U publication Critical patent/JPS5892733U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図はこの考案に係わる半導体装置の一実施例を示す
概要断面図、第２図Ａ−Ｃは同上装置の電極形成を工程
順に示す断面図である。 １・・・・・・シリコン半導体ウェハ、２・・曲拡散領
域、３・・・・・・コンタクトホール、４・・・・・・
シリコン酸化膜、５・・・・・・バリヤメタル層、６・
・曲金層、７・・・・・・金メッキ層、８・・・・・・
保護酸化膜、９・・・・・・ボンディングパット部。

Claims (1)

    【実用新案登録請求の範囲】
  1. 内部に機能領域を形成したシリコン半導体ウェハを有し
    、この半導体ウェハの表面に少なぐとも金層を含む複数
    の金属層からなる電極パターンを設け、この電極パター
    ンのボンディングパット部を除く表面を、シリコンを含
    む絶縁化合物による保護膜で被覆した半導体装置の電極
    構造において、前記保護膜診成に先立って電極パターン
    の表面を金メッキ層で被覆したことを特徴とする半導体
    装置の電極構造。
JP1981186609U 1981-12-14 1981-12-14 半導体装置の電極構造 Pending JPS5892733U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981186609U JPS5892733U (ja) 1981-12-14 1981-12-14 半導体装置の電極構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981186609U JPS5892733U (ja) 1981-12-14 1981-12-14 半導体装置の電極構造

Publications (1)

Publication Number Publication Date
JPS5892733U true JPS5892733U (ja) 1983-06-23

Family

ID=29988698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981186609U Pending JPS5892733U (ja) 1981-12-14 1981-12-14 半導体装置の電極構造

Country Status (1)

Country Link
JP (1) JPS5892733U (ja)

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