JPS60156747U - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS60156747U JPS60156747U JP4292984U JP4292984U JPS60156747U JP S60156747 U JPS60156747 U JP S60156747U JP 4292984 U JP4292984 U JP 4292984U JP 4292984 U JP4292984 U JP 4292984U JP S60156747 U JPS60156747 U JP S60156747U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- metal layers
- semiconductor equipment
- ceramic substrate
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第１図は従来の半導体装置の例を示す斜視図、第２図ａ
乃至Ｃは本考案の一実施例に関わるセラミック基板の製
造法を説明する各工程断面図、第３図は本考案の一実施
例を示す平面図である。
乃至Ｃは本考案の一実施例に関わるセラミック基板の製
造法を説明する各工程断面図、第３図は本考案の一実施
例を示す平面図である。
Claims (1)
- 半導体素子と、該半導体素子を搭載したセラミック基板
と、該セラミック基板上に施された複数゛ 本の金属
層と、この金属層と前記半導体素子の電極とを電気的に
接続する金属細線とを有する半導体装置において、前記
金属層は実質的に同一幅のパタ゛−ンで形成され、かつ
そのうちの少なくとも１本はそのすべてを絶縁被膜で覆
っていないことを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4292984U JPS60156747U (ja) | 1984-03-26 | 1984-03-26 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4292984U JPS60156747U (ja) | 1984-03-26 | 1984-03-26 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60156747U true JPS60156747U (ja) | 1985-10-18 |
Family
ID=30554123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4292984U Pending JPS60156747U (ja) | 1984-03-26 | 1984-03-26 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60156747U (ja) |
-
1984
- 1984-03-26 JP JP4292984U patent/JPS60156747U/ja active Pending
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