JPS6083258U - 樹脂封止型半導体装置 - Google Patents
樹脂封止型半導体装置Info
- Publication number
- JPS6083258U JPS6083258U JP1983176146U JP17614683U JPS6083258U JP S6083258 U JPS6083258 U JP S6083258U JP 1983176146 U JP1983176146 U JP 1983176146U JP 17614683 U JP17614683 U JP 17614683U JP S6083258 U JPS6083258 U JP S6083258U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- lead
- encapsulated semiconductor
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は従来のリードフレームの平面図、第2図は本考
案に係るリードフレームの平面図で、第3図はそのA−
A’線部分拡大断面図、第4図、第5図、第6図は本考
案に係るリードフレームにおけるリード線の配線例を示
す概略平面図で、第7図はその抵抗体を介した配線例を
示す概略平面図である。 2・・・リードフレーム、2b・・・リード部、3・・
・絶縁層、4・・・導電層、7・・・抵抗体。
案に係るリードフレームの平面図で、第3図はそのA−
A’線部分拡大断面図、第4図、第5図、第6図は本考
案に係るリードフレームにおけるリード線の配線例を示
す概略平面図で、第7図はその抵抗体を介した配線例を
示す概略平面図である。 2・・・リードフレーム、2b・・・リード部、3・・
・絶縁層、4・・・導電層、7・・・抵抗体。
Claims (2)
- (1)金属製のリードフレームを使用する半導体装置に
おいて、リードフレームの個々のリード部の表面上に絶
縁層及び導電層を交互に積層して形成し1本のリードに
複数の導電路を設けたことを特徴とする樹脂封止型半導
体装置。 - (2)実用新案登録請求の範囲第1項記載の半導体装置
においてリードフレームの個々のリード部の表面上に形
成されている導電層を抵抗体にしたことを特徴とする樹
脂封止型半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983176146U JPS6083258U (ja) | 1983-11-14 | 1983-11-14 | 樹脂封止型半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983176146U JPS6083258U (ja) | 1983-11-14 | 1983-11-14 | 樹脂封止型半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6083258U true JPS6083258U (ja) | 1985-06-08 |
Family
ID=30383035
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983176146U Pending JPS6083258U (ja) | 1983-11-14 | 1983-11-14 | 樹脂封止型半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6083258U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018152392A (ja) * | 2017-03-10 | 2018-09-27 | 三菱電機株式会社 | 半導体モジュールおよび電力変換装置 |
-
1983
- 1983-11-14 JP JP1983176146U patent/JPS6083258U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018152392A (ja) * | 2017-03-10 | 2018-09-27 | 三菱電機株式会社 | 半導体モジュールおよび電力変換装置 |
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