JPS5856452U - ハイブリツド型電子部品 - Google Patents
ハイブリツド型電子部品Info
- Publication number
- JPS5856452U JPS5856452U JP1981152301U JP15230181U JPS5856452U JP S5856452 U JPS5856452 U JP S5856452U JP 1981152301 U JP1981152301 U JP 1981152301U JP 15230181 U JP15230181 U JP 15230181U JP S5856452 U JPS5856452 U JP S5856452U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- hybrid electronic
- substrate
- electronic components
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は本考案の第1実施例を示す一部断面平面図、第
2図は第1図のI−I線に沿う部分的拡大断面図、第3
図は第1図の電子部品の斜視図、第4図は第1図の電子
部品の等価回路図、第5図は太考意の第2実施例を示す
一部断面平面図、第6図は第5図の■−■線に沿う部分
的拡大断面図、□第7図は第5図の電子部品の等価回路
図、第8図は本考案の第3実施例を示す一部断面平面図
、第 19図は第8図の■−■線に沿う部分的拡
大断面図、第10図は第8図における部品素子(コンデ
ンサ)の拡大断面図、第11図は第8図の電子部品の等
価回路図である。 1・・・・・・基板(放熱板)、2. 3. 4・・・
・・・リード、5・・・・・・半導体素子、7・・・・
・・部品素子(コア部材)、9.10・・・・・・金属
細線、11・・・・・・外装部材(樹脂材)、24・・
・・・・部品素子(コンデンサ)、26゜27・・・・
・・金属細線、30・・・・・・部品素子(コンデンサ
)、32. 33. 34・・曲金属細線。
2図は第1図のI−I線に沿う部分的拡大断面図、第3
図は第1図の電子部品の斜視図、第4図は第1図の電子
部品の等価回路図、第5図は太考意の第2実施例を示す
一部断面平面図、第6図は第5図の■−■線に沿う部分
的拡大断面図、□第7図は第5図の電子部品の等価回路
図、第8図は本考案の第3実施例を示す一部断面平面図
、第 19図は第8図の■−■線に沿う部分的拡
大断面図、第10図は第8図における部品素子(コンデ
ンサ)の拡大断面図、第11図は第8図の電子部品の等
価回路図である。 1・・・・・・基板(放熱板)、2. 3. 4・・・
・・・リード、5・・・・・・半導体素子、7・・・・
・・部品素子(コア部材)、9.10・・・・・・金属
細線、11・・・・・・外装部材(樹脂材)、24・・
・・・・部品素子(コンデンサ)、26゜27・・・・
・・金属細線、30・・・・・・部品素子(コンデンサ
)、32. 33. 34・・曲金属細線。
Claims (1)
- 基板と、基板近傍から外部に延びた複数のリードと、基
板上にマウントされた半導体素子及び半導体素子以外の
部品素子と1.”少くとも半導体素子とリードを電気的
に接続する複数の金属細線と、半導体素子を含む主要部
分を封止した外装部材とを具備したことを特徴とするハ
イブリッド型電子部品。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1981152301U JPS5856452U (ja) | 1981-10-13 | 1981-10-13 | ハイブリツド型電子部品 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1981152301U JPS5856452U (ja) | 1981-10-13 | 1981-10-13 | ハイブリツド型電子部品 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5856452U true JPS5856452U (ja) | 1983-04-16 |
Family
ID=29944956
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1981152301U Pending JPS5856452U (ja) | 1981-10-13 | 1981-10-13 | ハイブリツド型電子部品 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5856452U (ja) |
-
1981
- 1981-10-13 JP JP1981152301U patent/JPS5856452U/ja active Pending
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