JPS594648U - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPS594648U
JPS594648U JP9981682U JP9981682U JPS594648U JP S594648 U JPS594648 U JP S594648U JP 9981682 U JP9981682 U JP 9981682U JP 9981682 U JP9981682 U JP 9981682U JP S594648 U JPS594648 U JP S594648U
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
encapsulated semiconductor
substrate
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9981682U
Other languages
English (en)
Inventor
「あま」田 秀雄
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP9981682U priority Critical patent/JPS594648U/ja
Publication of JPS594648U publication Critical patent/JPS594648U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第1図は従来の樹脂封止型半導体装置の一例を示す一部
透視平面図、第2図は第1図A−A断面図、第3図は本
考案の前提となる半導体装置の一部透視平面図、第4図
は第3図B−B断面図、第5図は第3図半導体装置の製
造に用いられる樹脂成型金型の一例を示す側断面図、第
6図は本考案による半導体装置の一例を示す一部透視平
面図、第7図は第6図C−C断面図、第8図は本考案の
他の例を示す一部透視平面図、第9図は第8図り一り断
面図を示す。 1・・・・・・基板、2・・・・・・半導体ペレット、
3・・・・・・リード、11.13・・・・・・第1の
樹脂層、12.14・・・・・・第2の樹脂層。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基板上に載置した半導体ペレットと、一端を半導体ペレ
    ットの近傍に配置したリードとを電気的に接続し、上記
    基板の少くとも裏面に第1の樹脂層を、その余の部分に
    第2の樹脂層をそれぞれ形成したことを特徴とする樹脂
    封止型半導体装置。
JP9981682U 1982-06-30 1982-06-30 樹脂封止型半導体装置 Pending JPS594648U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9981682U JPS594648U (ja) 1982-06-30 1982-06-30 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9981682U JPS594648U (ja) 1982-06-30 1982-06-30 樹脂封止型半導体装置

Publications (1)

Publication Number Publication Date
JPS594648U true JPS594648U (ja) 1984-01-12

Family

ID=30236385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9981682U Pending JPS594648U (ja) 1982-06-30 1982-06-30 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JPS594648U (ja)

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