JPS6033452U - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPS6033452U
JPS6033452U JP12384583U JP12384583U JPS6033452U JP S6033452 U JPS6033452 U JP S6033452U JP 12384583 U JP12384583 U JP 12384583U JP 12384583 U JP12384583 U JP 12384583U JP S6033452 U JPS6033452 U JP S6033452U
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
encapsulated semiconductor
island
recorded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12384583U
Other languages
English (en)
Inventor
明石　進一
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP12384583U priority Critical patent/JPS6033452U/ja
Publication of JPS6033452U publication Critical patent/JPS6033452U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来のチップ型半導体装置を示す断面図、第２
図は本考案の一実施例を示す断面図、第３図は本実施例
でつかわれたリードフレームの平面図である。 １・・・半導体素子、２，２′・・・アイランド部、３
．３′・・・外部リード、４・・・ボンディングワイヤ
ー、５，５′・・・樹脂、５″・・・樹脂の境界部、１
゜・・・リードフレーム。

Claims (1)

    【実用新案登録請求の範囲】
  1. 外部リード下面及び半導体素子を搭載するアイランド下
    面が露出する様に樹脂封止を行ったことを特徴とする樹
    脂封止型半導体装置。
JP12384583U 1983-08-10 1983-08-10 樹脂封止型半導体装置 Pending JPS6033452U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12384583U JPS6033452U (ja) 1983-08-10 1983-08-10 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12384583U JPS6033452U (ja) 1983-08-10 1983-08-10 樹脂封止型半導体装置

Publications (1)

Publication Number Publication Date
JPS6033452U true JPS6033452U (ja) 1985-03-07

Family

ID=30282544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12384583U Pending JPS6033452U (ja) 1983-08-10 1983-08-10 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JPS6033452U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62134945A (ja) * 1985-12-06 1987-06-18 Sony Corp モ−ルドトランジスタ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62134945A (ja) * 1985-12-06 1987-06-18 Sony Corp モ−ルドトランジスタ

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