JPH01113366U - - Google Patents

Info

Publication number
JPH01113366U
JPH01113366U JP865988U JP865988U JPH01113366U JP H01113366 U JPH01113366 U JP H01113366U JP 865988 U JP865988 U JP 865988U JP 865988 U JP865988 U JP 865988U JP H01113366 U JPH01113366 U JP H01113366U
Authority
JP
Japan
Prior art keywords
diffusion layer
semiconductor substrate
integrated circuit
contact
mos integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP865988U
Other languages
English (en)
Other versions
JPH0749798Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP865988U priority Critical patent/JPH0749798Y2/ja
Publication of JPH01113366U publication Critical patent/JPH01113366U/ja
Application granted granted Critical
Publication of JPH0749798Y2 publication Critical patent/JPH0749798Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図ａは本考案の一実施例に係るボンデイン
グパツド近傍の部分平面図、同図ｂは同図ａのＡ
―Ａ断面図、第２図ａは従来のＭＯＳ集積回路の
ボンデイングパツド近傍の部分平面図、同図ｂは
同図ａのＡ―Ａ断面図である。 １……半導体基板、２……拡散層、３……酸化
膜、４……ボンデイングパツド、５……拡散層上
の金属導体、６……貫通コンタクト、７……配線
導体。

Claims (1)

    【実用新案登録請求の範囲】
  1. 多数のボンデイングパツドが設けられている半
    導体基板を有するＭＯＳ集積回路において、前記
    半導体基板と異なる導電型の不純物拡散層が前記
    ボンデイングパツドの周りを囲むように埋め込ま
    れ、さらに、前記拡散層の上の金属導体と拡散層
    とを接触させるためのコンタクトが設けられてい
    ることを特徴とするＭＯＳ集積回路。
JP865988U 1988-01-25 1988-01-25 Ｍｏｓ集積回路 Expired - Lifetime JPH0749798Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP865988U JPH0749798Y2 (ja) 1988-01-25 1988-01-25 Ｍｏｓ集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP865988U JPH0749798Y2 (ja) 1988-01-25 1988-01-25 Ｍｏｓ集積回路

Publications (2)

Publication Number Publication Date
JPH01113366U true JPH01113366U (ja) 1989-07-31
JPH0749798Y2 JPH0749798Y2 (ja) 1995-11-13

Family

ID=31214733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP865988U Expired - Lifetime JPH0749798Y2 (ja) 1988-01-25 1988-01-25 Ｍｏｓ集積回路

Country Status (1)

Country Link
JP (1) JPH0749798Y2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6133611B2 (ja) * 2013-02-06 2017-05-24 エスアイアイ・セミコンダクタ株式会社 半導体装置

Also Published As

Publication number Publication date
JPH0749798Y2 (ja) 1995-11-13

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