JPS62170648U - - Google Patents
Info
- Publication number
- JPS62170648U JPS62170648U JP5791286U JP5791286U JPS62170648U JP S62170648 U JPS62170648 U JP S62170648U JP 5791286 U JP5791286 U JP 5791286U JP 5791286 U JP5791286 U JP 5791286U JP S62170648 U JPS62170648 U JP S62170648U
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- electrode wiring
- diffusion region
- integrated circuit
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims 3
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
第1図及び第2図は夫々本考案の第1の実施例
を示す平面図及び―線断面図、第3図及び第
4図は夫々本考案の第2の実施例を示す平面図及
び―線断面図、第5図及び第6図は夫々本考
案の第3の実施例を示す平面図及び―線断面
図、第7図及び第8図は夫々従来例を示す平面図
及び―線断面図である。 21はP型半導体基板、24は島領域、26は
トンネル抵抗領域、27はP型ベース抵抗領域、
29はボンデイングパツド、30は電極配線、3
4はアロイスパイク、31,32,33はコンタ
クトホールである。
を示す平面図及び―線断面図、第3図及び第
4図は夫々本考案の第2の実施例を示す平面図及
び―線断面図、第5図及び第6図は夫々本考
案の第3の実施例を示す平面図及び―線断面
図、第7図及び第8図は夫々従来例を示す平面図
及び―線断面図である。 21はP型半導体基板、24は島領域、26は
トンネル抵抗領域、27はP型ベース抵抗領域、
29はボンデイングパツド、30は電極配線、3
4はアロイスパイク、31,32,33はコンタ
クトホールである。
Claims (1)
- 外部接続用のボンデイングパツドと該ボンデイ
ングパツドと離間して形成した少なくとも1つの
拡散領域と前記ボンデイングパツドと前記拡散領
域とを電気的に接続するための電極配線とを具備
する半導体集積回路において、前記電極配線を前
記ボンデイングパツド近傍で切断し、前記ボンデ
イングパツドと前記電極配線とを1つの島領域表
面に形成したP型又はN型の拡散領域で接続した
ことを特徴とする半導体集積回路。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5791286U JPS62170648U (ja) | 1986-04-17 | 1986-04-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5791286U JPS62170648U (ja) | 1986-04-17 | 1986-04-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62170648U true JPS62170648U (ja) | 1987-10-29 |
Family
ID=30888037
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5791286U Pending JPS62170648U (ja) | 1986-04-17 | 1986-04-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62170648U (ja) |
-
1986
- 1986-04-17 JP JP5791286U patent/JPS62170648U/ja active Pending