JPH0165148U - - Google Patents
Info
- Publication number
- JPH0165148U JPH0165148U JP16013387U JP16013387U JPH0165148U JP H0165148 U JPH0165148 U JP H0165148U JP 16013387 U JP16013387 U JP 16013387U JP 16013387 U JP16013387 U JP 16013387U JP H0165148 U JPH0165148 U JP H0165148U
- Authority
- JP
- Japan
- Prior art keywords
- lower layer
- bonding pad
- layer
- insulating film
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010410 layer Substances 0.000 claims 12
- 239000011229 interlayer Substances 0.000 claims 3
- 239000004642 Polyimide Substances 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図及び第2図は夫々本考案を説明する為の
断面図及び平面図、第3図は本考案の第2の実施
例を説明する為の平面図、第4図は従来例を説明
する為の断面図である。 11は半導体基板、13は下層のボンデイング
パツド、14は下層の延在部、16は上層のボン
デイングパツド、21は上層のボンデイングパツ
ド16の側端部である。
断面図及び平面図、第3図は本考案の第2の実施
例を説明する為の平面図、第4図は従来例を説明
する為の断面図である。 11は半導体基板、13は下層のボンデイング
パツド、14は下層の延在部、16は上層のボン
デイングパツド、21は上層のボンデイングパツ
ド16の側端部である。
Claims (1)
- 下層のボンデイングパツドと、この下層のボン
デイングパツドから延在し前記下層のボンデイン
グパツドと同層又はそれより上層の配線層と接続
する下層の延在部と、前記下層のボンデイングパ
ツド及び下層の延在部を覆うポリイミド系の層間
絶縁膜と、該層間絶縁膜のスルーホールを介して
前記下層のボンデイングパツドと接続しその側端
部が前記下層のボンデイングパツドによる段差を
覆うように前記層間絶縁膜上を延在する上層のボ
ンデイングパツドとを具備することを特徴とする
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987160133U JPH0642340Y2 (ja) | 1987-10-20 | 1987-10-20 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987160133U JPH0642340Y2 (ja) | 1987-10-20 | 1987-10-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0165148U true JPH0165148U (ja) | 1989-04-26 |
JPH0642340Y2 JPH0642340Y2 (ja) | 1994-11-02 |
Family
ID=31441933
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987160133U Expired - Lifetime JPH0642340Y2 (ja) | 1987-10-20 | 1987-10-20 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0642340Y2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4740536B2 (ja) * | 2003-11-26 | 2011-08-03 | ローム株式会社 | 半導体装置およびその製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5996851U (ja) * | 1982-12-20 | 1984-06-30 | 日本電気株式会社 | 半導体装置 |
JPS6074658A (ja) * | 1983-09-30 | 1985-04-26 | Toshiba Corp | 半導体集積回路装置 |
-
1987
- 1987-10-20 JP JP1987160133U patent/JPH0642340Y2/ja not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5996851U (ja) * | 1982-12-20 | 1984-06-30 | 日本電気株式会社 | 半導体装置 |
JPS6074658A (ja) * | 1983-09-30 | 1985-04-26 | Toshiba Corp | 半導体集積回路装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4740536B2 (ja) * | 2003-11-26 | 2011-08-03 | ローム株式会社 | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPH0642340Y2 (ja) | 1994-11-02 |