JPS6310571U - - Google Patents
Info
- Publication number
- JPS6310571U JPS6310571U JP10377786U JP10377786U JPS6310571U JP S6310571 U JPS6310571 U JP S6310571U JP 10377786 U JP10377786 U JP 10377786U JP 10377786 U JP10377786 U JP 10377786U JP S6310571 U JPS6310571 U JP S6310571U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit
- substrate
- substrate via
- conductive connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案による半導体素子の実装構造を
示す断面図、第２図は従来の実装構造の断面図で
ある。 １……第１の半導体素子、２……基板、３……
導電性コネクタ、４……半田、５……配線、６…
…第２の半導体素子、７……バンプ。
示す断面図、第２図は従来の実装構造の断面図で
ある。 １……第１の半導体素子、２……基板、３……
導電性コネクタ、４……半田、５……配線、６…
…第２の半導体素子、７……バンプ。
Claims (1)
- 第１の半導体素子を導電性コネクタを介して基
板に電気的に接続し、前記第１の半導体素子と前
記基板との間に第２の半導体素子を配置し、該第
２の半導体素子の回路が形成された面はバンプを
介して前記第１の半導体素子または前記基板のど
ちらか一方に、回路が形成されていない面は接着
部材を介して他方に接続したことを特徴とする半
導体素子の実装構造。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10377786U JPS6310571U (ja) | 1986-07-08 | 1986-07-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10377786U JPS6310571U (ja) | 1986-07-08 | 1986-07-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6310571U true JPS6310571U (ja) | 1988-01-23 |
Family
ID=30976657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10377786U Pending JPS6310571U (ja) | 1986-07-08 | 1986-07-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6310571U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8748229B2 (en) | 2008-06-11 | 2014-06-10 | Fujitsu Semiconductor Limited | Manufacturing method including deformation of supporting board to accommodate semiconductor device |
-
1986
- 1986-07-08 JP JP10377786U patent/JPS6310571U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8748229B2 (en) | 2008-06-11 | 2014-06-10 | Fujitsu Semiconductor Limited | Manufacturing method including deformation of supporting board to accommodate semiconductor device |