JPS62152444U - - Google Patents

Info

Publication number
JPS62152444U
JPS62152444U JP1986039139U JP3913986U JPS62152444U JP S62152444 U JPS62152444 U JP S62152444U JP 1986039139 U JP1986039139 U JP 1986039139U JP 3913986 U JP3913986 U JP 3913986U JP S62152444 U JPS62152444 U JP S62152444U
Authority
JP
Japan
Prior art keywords
substrate
semiconductor element
thermal expansion
buffer member
registration request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986039139U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986039139U priority Critical patent/JPS62152444U/ja
Publication of JPS62152444U publication Critical patent/JPS62152444U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案による半導体装置の一実施例の
断面図、第２図および第３図はそれぞれ本考案に
よる半導体装置の他の実施例の断面図、第４図は
従来の半導体装置の断面図である。 １…半導体素子、２…基板、３…配線、４…バ
ンプ、５…電極、６…セラミツク板、７…プリン
ト基板、８…半田、９…ＳｉＣ基板、１０…リー
ド線。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子と基板との間に前記両者の各熱膨脹
    係数の中間の熱膨脹係数を有するバツフアー部材
    を配置し、該バツフアー部材と前記半導体素子お
    よび前記基板とを導電性結合部材により接続して
    成ることを特徴とする半導体装置。
JP1986039139U 1986-03-19 1986-03-19 Pending JPS62152444U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986039139U JPS62152444U (ja) 1986-03-19 1986-03-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986039139U JPS62152444U (ja) 1986-03-19 1986-03-19

Publications (1)

Publication Number Publication Date
JPS62152444U true JPS62152444U (ja) 1987-09-28

Family

ID=30852035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986039139U Pending JPS62152444U (ja) 1986-03-19 1986-03-19

Country Status (1)

Country Link
JP (1) JPS62152444U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08153750A (ja) * 1994-08-31 1996-06-11 Nec Corp 電子デバイス組立体およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08153750A (ja) * 1994-08-31 1996-06-11 Nec Corp 電子デバイス組立体およびその製造方法

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