JPS6115743U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6115743U
JPS6115743U JP9342785U JP9342785U JPS6115743U JP S6115743 U JPS6115743 U JP S6115743U JP 9342785 U JP9342785 U JP 9342785U JP 9342785 U JP9342785 U JP 9342785U JP S6115743 U JPS6115743 U JP S6115743U
Authority
JP
Japan
Prior art keywords
metallized layer
semiconductor element
metallized
lead wire
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9342785U
Other languages
English (en)
Other versions
JPS6144434Y2 (ja
Inventor
裕 平野
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP9342785U priority Critical patent/JPS6115743U/ja
Publication of JPS6115743U publication Critical patent/JPS6115743U/ja
Application granted granted Critical
Publication of JPS6144434Y2 publication Critical patent/JPS6144434Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】 第１図及び第２図は従来の半導体装置の構造を示す平面
図及び断面図、第３図及び第４図は本考案による半導体
装置の構造を示す平面図、第５図及び第６図は本考案の
他の実施例による半導体装置の構造を示す平面図である
。 図面において、１１・・・絶縁基板、１２・・・半導体
素子、１３，１５，１６・・・メタライズ層、１７，１
７’，１８．１９・・・外部接続端子、２ｏ・・・枠体
、２１・・・鑞材、１４，１４’，２２．２２’・・・
リード線、２３・・・分離領域、１３ｃ・・・メタライ
ズ層、１３−ｄ・・・リード線固着部、６１・・・分離
領域、６１−ａ・・・分離領域６１の外側端。

Claims (1)

    【実用新案登録請求の範囲】
  1. 絶縁基板と：前記絶縁基板上に形成されたメタライズ層
    と、前記メタライズ層上に固着された半導体素子と、前
    記半導体素子から導出され前記メタライズ層と一体とな
    ったメタライズ部に接続されたリード線−と、前記半導
    体素子の周囲に配設された封止部材とを有する半導体装
    置において、前記半導体素子が固着されるメタライズ層
    の素子固着部とリード線接続部との間に、非メタライズ
    部を設けると共に、前記リード線を接続したメタライズ
    部が前記メタライズ層の素子固着部より完全に分離して
    島状を形成する位置に前記封止部材を設けたことを特徴
    とする半導体装置。
JP9342785U 1985-06-20 1985-06-20 半導体装置 Granted JPS6115743U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9342785U JPS6115743U (ja) 1985-06-20 1985-06-20 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9342785U JPS6115743U (ja) 1985-06-20 1985-06-20 半導体装置

Publications (2)

Publication Number Publication Date
JPS6115743U true JPS6115743U (ja) 1986-01-29
JPS6144434Y2 JPS6144434Y2 (ja) 1986-12-15

Family

ID=30651098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9342785U Granted JPS6115743U (ja) 1985-06-20 1985-06-20 半導体装置

Country Status (1)

Country Link
JP (1) JPS6115743U (ja)

Also Published As

Publication number Publication date
JPS6144434Y2 (ja) 1986-12-15

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