JPS5822741U - 半導体パツケ−ジ - Google Patents

半導体パツケ−ジ

Info

Publication number
JPS5822741U
JPS5822741U JP1981117854U JP11785481U JPS5822741U JP S5822741 U JPS5822741 U JP S5822741U JP 1981117854 U JP1981117854 U JP 1981117854U JP 11785481 U JP11785481 U JP 11785481U JP S5822741 U JPS5822741 U JP S5822741U
Authority
JP
Japan
Prior art keywords
semiconductor package
lead
insulating substrate
metallized
metallized layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1981117854U
Other languages
English (en)
Other versions
JPS635238Y2 (ja
Inventor
西川　美彦
Original Assignee
京セラ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京セラ株式会社 filed Critical 京セラ株式会社
Priority to JP1981117854U priority Critical patent/JPS5822741U/ja
Publication of JPS5822741U publication Critical patent/JPS5822741U/ja
Application granted granted Critical
Publication of JPS635238Y2 publication Critical patent/JPS635238Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来の半導体パッケージの断面図であり、第２
図は本考案の一実施例を示す断面図である。 １：絶縁基板、２ｂ＝メタライズ層、２ａ、　　２ｃ：
メタライズリード、３：外部リード、１０ニスルーホー
ル。

Claims (1)

    【実用新案登録請求の範囲】
  1. 絶縁基板上面に形成されたメタライズ層に外部リードが
    ロウ接されて成る半導体パッケージにおいて、半導体、
    素子が接続されるメタライズリードがスルーホールを介
    して絶縁基板の側面に導出され、且つこの導出部と絶縁
    基板上面の前記メタライズ層とを接続するようにメタラ
    イズリードが延長され、これにより迂回導電路が形成さ
    れたことを特徴とする半導体パッケージ。
JP1981117854U 1981-08-07 1981-08-07 半導体パツケ−ジ Granted JPS5822741U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981117854U JPS5822741U (ja) 1981-08-07 1981-08-07 半導体パツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981117854U JPS5822741U (ja) 1981-08-07 1981-08-07 半導体パツケ−ジ

Publications (2)

Publication Number Publication Date
JPS5822741U true JPS5822741U (ja) 1983-02-12
JPS635238Y2 JPS635238Y2 (ja) 1988-02-12

Family

ID=29912006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981117854U Granted JPS5822741U (ja) 1981-08-07 1981-08-07 半導体パツケ−ジ

Country Status (1)

Country Link
JP (1) JPS5822741U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045045A (ja) * 1983-08-23 1985-03-11 Shinko Electric Ind Co Ltd 多層セラミックパッケ−ジ

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5318962A (en) * 1976-08-05 1978-02-21 Nec Corp Semiconductor package
JPS5660038A (en) * 1980-10-20 1981-05-23 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5318962A (en) * 1976-08-05 1978-02-21 Nec Corp Semiconductor package
JPS5660038A (en) * 1980-10-20 1981-05-23 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045045A (ja) * 1983-08-23 1985-03-11 Shinko Electric Ind Co Ltd 多層セラミックパッケ−ジ

Also Published As

Publication number Publication date
JPS635238Y2 (ja) 1988-02-12

Similar Documents

Publication Publication Date Title
JPS5822741U (ja) 半導体パツケ−ジ
JPS58120662U (ja) チツプキヤリヤ−
JPS59132641U (ja) 半導体装置用基板
JPS6338328U (ja)
JPS60151137U (ja) チツプキヤリア
JPS58109254U (ja) フエ−スダウン接続形チツプ用チツプキヤリヤ−
JPS58166041U (ja) 半導体装置
JPS59171372U (ja) 薄型回路基板
JPS58122459U (ja) 半導体素子外囲器
JPS6094836U (ja) 半導体装置
JPS60106375U (ja) 外部リ−ド端子の取付構造
JPS5860942U (ja) 混成集積回路装置
JPS6037240U (ja) 混成集積回路
JPS6027438U (ja) 混成集積回路装置
JPS6037241U (ja) 電子機器
JPS60931U (ja) 半導体装置
JPS63132477U (ja)
JPS6142847U (ja) 半導体装置用パツケ−ジ
JPS5899841U (ja) 半導体装置
JPS59189232U (ja) 電子部品
JPS5881940U (ja) 半導体素子の取付構造
JPS58184844U (ja) セラミツクパツケ−ジ
JPS6310571U (ja)
JPS5954956U (ja) 半導体パツケ−ジ
JPS59131158U (ja) チツプキヤリヤ−