JPS5860942U - 混成集積回路装置 - Google Patents

混成集積回路装置

Info

Publication number
JPS5860942U
JPS5860942U JP1981157286U JP15728681U JPS5860942U JP S5860942 U JPS5860942 U JP S5860942U JP 1981157286 U JP1981157286 U JP 1981157286U JP 15728681 U JP15728681 U JP 15728681U JP S5860942 U JPS5860942 U JP S5860942U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
heat sink
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1981157286U
Other languages
English (en)
Other versions
JPS629738Y2 (ja
Inventor
栄治 小林
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP1981157286U priority Critical patent/JPS5860942U/ja
Publication of JPS5860942U publication Critical patent/JPS5860942U/ja
Application granted granted Critical
Publication of JPS629738Y2 publication Critical patent/JPS629738Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来の混成集積回路装置を示す断面図、第２図
および第３図は従来装置の製造段階を示す部分断面図、
第４図および第５図はこの考案の一実施例を示す部分断
面図である。 図において、１は絶縁基板、２は導電体、３はヒートシ
ンク、３ａは凹部、３ｄは凹部のテーパ部である。なお
、図中同一符号は同一または相当部分を示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. 一主面に半導体が設けられた絶縁基板をヒートシンクへ
    固定し、前記導電体と前記ヒートシンクに設けられた凹
    部間をリード線で半田接続して成る混成集積回路装置に
    おいて、前記凹部の内壁へテーパーを付けたことを特徴
    とする混成集積回路装置。
JP1981157286U 1981-10-20 1981-10-20 混成集積回路装置 Granted JPS5860942U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981157286U JPS5860942U (ja) 1981-10-20 1981-10-20 混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981157286U JPS5860942U (ja) 1981-10-20 1981-10-20 混成集積回路装置

Publications (2)

Publication Number Publication Date
JPS5860942U true JPS5860942U (ja) 1983-04-25
JPS629738Y2 JPS629738Y2 (ja) 1987-03-06

Family

ID=29949814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981157286U Granted JPS5860942U (ja) 1981-10-20 1981-10-20 混成集積回路装置

Country Status (1)

Country Link
JP (1) JPS5860942U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5472961A (en) * 1977-11-24 1979-06-11 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5472961A (en) * 1977-11-24 1979-06-11 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS629738Y2 (ja) 1987-03-06

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