JPS59112954U - 絶縁物封止半導体装置 - Google Patents

絶縁物封止半導体装置

Info

Publication number
JPS59112954U
JPS59112954U JP678983U JP678983U JPS59112954U JP S59112954 U JPS59112954 U JP S59112954U JP 678983 U JP678983 U JP 678983U JP 678983 U JP678983 U JP 678983U JP S59112954 U JPS59112954 U JP S59112954U
Authority
JP
Japan
Prior art keywords
insulator
wide
external lead
semiconductor device
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP678983U
Other languages
English (en)
Other versions
JPH0414939Y2 (ja
Inventor
都外川　「峰」秀
Original Assignee
サンケン電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by サンケン電気株式会社 filed Critical サンケン電気株式会社
Priority to JP678983U priority Critical patent/JPS59112954U/ja
Publication of JPS59112954U publication Critical patent/JPS59112954U/ja
Application granted granted Critical
Publication of JPH0414939Y2 publication Critical patent/JPH0414939Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図〜第４図は従来の絶縁物封止半導体装置を示す。 第５図〜第９図は本考案に係る絶縁物封止半導体装置を
示す。第１図、第３図、第５図および第７図は平面図で
、第２図、第４図、第６図および第８図はそれぞれのＡ
−Ａ線断面図である。 第９図も平面図である。 １はパワートランジスタチップ（半導体素子）、２は放
熱板、３．　４．　５は外部リード、３ａ、　　４ａ。 ５ａは外部リードの幅広部、３ｂ、４ｂ、５ｂは外部リ
ードの幅狭部、４ｃ、５ｃは外部リードの内部リード線
用端子部、６，７は内部リード線、８は樹脂体（絶縁物
）、９は連結部材残存部、１０゜１１は樹脂体の段差部
、１２は樹脂体の凹部。 第２図 ツー− 乙　　　！ ノ／

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子が絶縁物によって封止され、少なくとも第１
    、第２および第３の外部リードが第１の外部リードを中
    央に配して前記絶縁物から並列に導出され、前記第１、
    第２および第３の外部リードはそれぞれ前記絶縁部から
    の導出側が幅広部で先端側か幅狭部である構造において
    、前記第１の外部リードの前記幅広部は前記第１の外部
    リードの前記幅狭部を前記絶縁物まで延長した部分の両
    側に張出した形状で幅広になっており、前記第２、第３
    の外部リードの前記幅広部のうち少なくとも前記絶縁物
    表面と隣接する部分はそれぞれ前記第２、第３の外部リ
    ードの前記幅狭部を前記絶縁物まで延長した部分の前記
    第１の外部リードに対面する側とは反対側にのみ張出し
    た形状で幅広になっていることを特徴とする絶縁物封止
    半導体装置。
JP678983U 1983-01-21 1983-01-21 絶縁物封止半導体装置 Granted JPS59112954U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP678983U JPS59112954U (ja) 1983-01-21 1983-01-21 絶縁物封止半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP678983U JPS59112954U (ja) 1983-01-21 1983-01-21 絶縁物封止半導体装置

Publications (2)

Publication Number Publication Date
JPS59112954U true JPS59112954U (ja) 1984-07-30
JPH0414939Y2 JPH0414939Y2 (ja) 1992-04-03

Family

ID=30138329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP678983U Granted JPS59112954U (ja) 1983-01-21 1983-01-21 絶縁物封止半導体装置

Country Status (1)

Country Link
JP (1) JPS59112954U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6457654U (ja) * 1987-10-05 1989-04-10

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53112275U (ja) * 1977-02-10 1978-09-07
JPS5584957U (ja) * 1978-12-04 1980-06-11

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53112275U (ja) * 1977-02-10 1978-09-07
JPS5584957U (ja) * 1978-12-04 1980-06-11

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6457654U (ja) * 1987-10-05 1989-04-10

Also Published As

Publication number Publication date
JPH0414939Y2 (ja) 1992-04-03

Similar Documents

Publication Publication Date Title
JPS5827934U (ja) 半導体装置
JPS59112954U (ja) 絶縁物封止半導体装置
JPS59115653U (ja) 絶縁物封止半導体装置
JPS6371547U (ja)
JPS59112951U (ja) 絶縁物封止半導体装置
JPS59117160U (ja) 絶縁物封止半導体装置
JPS63155650U (ja)
JPS60130649U (ja) 樹脂封止型半導体装置
JPS619840U (ja) 樹脂封止型半導体装置
JPH0379442U (ja)
JPH03122543U (ja)
JPS5933254U (ja) 半導体装置
JPS6117752U (ja) テ−プキヤリア半導体装置
JPS59192850U (ja) 半導体装置
JPS59117156U (ja) 絶縁物封止半導体装置
JPS63187330U (ja)
JPS61123544U (ja)
JPS6142853U (ja) 樹脂封止型半導体装置
JPS609226U (ja) 半導体の実装用パツケ−ジ
JPS5842940U (ja) 混成集積回路装置
JPS60125754U (ja) 半導体装置
JPH0379443U (ja)
JPS594644U (ja) 樹脂モ−ルド半導体装置
JPS60118932U (ja) 端子付端子板
JPS6094836U (ja) 半導体装置