JPS5945929U - 半導体素子の実装構造 - Google Patents

半導体素子の実装構造

Info

Publication number
JPS5945929U
JPS5945929U JP1982142031U JP14203182U JPS5945929U JP S5945929 U JPS5945929 U JP S5945929U JP 1982142031 U JP1982142031 U JP 1982142031U JP 14203182 U JP14203182 U JP 14203182U JP S5945929 U JPS5945929 U JP S5945929U
Authority
JP
Japan
Prior art keywords
main surface
mounting structure
semiconductor element
element mounting
conductor pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1982142031U
Other languages
English (en)
Other versions
JPH019160Y2 (ja
Inventor
鳥羽　進
博 渡部
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP1982142031U priority Critical patent/JPS5945929U/ja
Publication of JPS5945929U publication Critical patent/JPS5945929U/ja
Application granted granted Critical
Publication of JPH019160Y2 publication Critical patent/JPH019160Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来構造を示すものでありａは断面図、ｂは同
図ａをｘ−ｘ’から見た平面図、第２図は本考案の実施
例を示すものでありａは断面図、ｂは同図ａをＹ−Ｙ’
から見た平面図である。 １・・・配線導体、２・・・基板、３・・・半導体素子
、４・・・ハンダパンフミ５・・・導電性スルーホール
、６・・・導電端子。

Claims (1)

    【実用新案登録請求の範囲】
  1. 基板の一主表面上に形成された導体パターンにフェスタ
    ウンボンデイング形半導体素子を該素子の電極を介して
    搭載するものにおいて、該導体パターンを前記−主表面
    上にて素子搭載領域外に導かれる配線導体と、素子搭載
    領域内にて前記−主表面から他の主表面に導電性スルー
    ホールを介して導かれる導電端子とから構成することを
    特徴とする半導体素子の実装構造。
JP1982142031U 1982-09-20 1982-09-20 半導体素子の実装構造 Granted JPS5945929U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982142031U JPS5945929U (ja) 1982-09-20 1982-09-20 半導体素子の実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982142031U JPS5945929U (ja) 1982-09-20 1982-09-20 半導体素子の実装構造

Publications (2)

Publication Number Publication Date
JPS5945929U true JPS5945929U (ja) 1984-03-27
JPH019160Y2 JPH019160Y2 (ja) 1989-03-13

Family

ID=30317485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982142031U Granted JPS5945929U (ja) 1982-09-20 1982-09-20 半導体素子の実装構造

Country Status (1)

Country Link
JP (1) JPS5945929U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5761853U (ja) * 1980-09-30 1982-04-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5761853U (ja) * 1980-09-30 1982-04-13

Also Published As

Publication number Publication date
JPH019160Y2 (ja) 1989-03-13

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