JPH04269873A - 逆シリサイドｔ型ゲート構造を有するトランジスタ - Google Patents

逆シリサイドｔ型ゲート構造を有するトランジスタ

Info

Publication number
JPH04269873A
JPH04269873A JP3320835A JP32083591A JPH04269873A JP H04269873 A JPH04269873 A JP H04269873A JP 3320835 A JP3320835 A JP 3320835A JP 32083591 A JP32083591 A JP 32083591A JP H04269873 A JPH04269873 A JP H04269873A
Authority
JP
Japan
Prior art keywords
gate structure
layer
source
gate
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3320835A
Other languages
English (en)
Japanese (ja)
Inventor
Min-Liang Chen
ミン−リアン　チェン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of JPH04269873A publication Critical patent/JPH04269873A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H10D30/0229—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET forming drain regions and lightly-doped drain [LDD] simultaneously, e.g. using implantation through a T-shaped mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
JP3320835A 1990-12-07 1991-12-05 逆シリサイドｔ型ゲート構造を有するトランジスタ Pending JPH04269873A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62478590A 1990-12-07 1990-12-07
US624785 1990-12-07

Publications (1)

Publication Number Publication Date
JPH04269873A true JPH04269873A (ja) 1992-09-25

Family

ID=24503301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3320835A Pending JPH04269873A (ja) 1990-12-07 1991-12-05 逆シリサイドｔ型ゲート構造を有するトランジスタ

Country Status (4)

Country Link
US (1) US5290720A (enExample)
EP (1) EP0490535B1 (enExample)
JP (1) JPH04269873A (enExample)
DE (1) DE69121535T2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
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KR100396895B1 (ko) * 2001-08-02 2003-09-02 삼성전자주식회사 Ｌ자형 스페이서를 채용한 반도체 소자의 제조 방법

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JPH06260497A (ja) * 1993-03-05 1994-09-16 Nippon Steel Corp 半導体装置及びその製造方法
JPH06275655A (ja) * 1993-03-24 1994-09-30 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5656543A (en) * 1995-02-03 1997-08-12 National Semiconductor Corporation Fabrication of integrated circuits with borderless vias
US5757077A (en) * 1995-02-03 1998-05-26 National Semiconductor Corporation Integrated circuits with borderless vias
US5858875A (en) * 1995-02-03 1999-01-12 National Semiconductor Corporation Integrated circuits with borderless vias
US5686357A (en) * 1995-07-10 1997-11-11 Micron Technology, Inc. Method for forming a contact during the formation of a semiconductor device
US5714413A (en) * 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
KR0166824B1 (ko) * 1995-12-19 1999-02-01 문정환 반도체 소자의 제조방법
US5739066A (en) * 1996-09-17 1998-04-14 Micron Technology, Inc. Semiconductor processing methods of forming a conductive gate and line
US5953596A (en) * 1996-12-19 1999-09-14 Micron Technology, Inc. Methods of forming thin film transistors
US5817562A (en) * 1997-01-24 1998-10-06 Taiwan Semiconductor Manufacturing Company, Ltd Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)
US20020137890A1 (en) * 1997-03-31 2002-09-26 Genentech, Inc. Secreted and transmembrane polypeptides and nucleic acids encoding the same
US5930642A (en) * 1997-06-09 1999-07-27 Advanced Micro Devices, Inc. Transistor with buried insulative layer beneath the channel region
US6218276B1 (en) 1997-12-22 2001-04-17 Lsi Logic Corporation Silicide encapsulation of polysilicon gate and interconnect
EP0951061A3 (en) * 1998-03-31 2003-07-09 Interuniversitair Microelektronica Centrum Vzw Method for forming a FET
US6037233A (en) * 1998-04-27 2000-03-14 Lsi Logic Corporation Metal-encapsulated polysilicon gate and interconnect
US6380039B2 (en) * 1998-05-06 2002-04-30 Interuniversitair Microelektronica Centrum (Imec Vzw) Method for forming a FET having L-shaped insulating spacers
US6143611A (en) * 1998-07-30 2000-11-07 Micron Technology, Inc. Semiconductor processing methods, methods of forming electronic components, and transistors
US6235598B1 (en) 1998-11-13 2001-05-22 Intel Corporation Method of using thick first spacers to improve salicide resistance on polysilicon gates
US6150266A (en) * 1999-01-28 2000-11-21 Vlsi Technology, Inc. Local interconnect formed using silicon spacer
US6235597B1 (en) * 1999-08-06 2001-05-22 International Business Machines Corporation Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication
US6294480B1 (en) * 1999-11-19 2001-09-25 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer with a disposable organic top coating
US6251762B1 (en) 1999-12-09 2001-06-26 Intel Corporation Method and device for improved salicide resistance on polysilicon gates
US6346468B1 (en) * 2000-02-11 2002-02-12 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer using a disposable polysilicon spacer
US6406986B1 (en) * 2000-06-26 2002-06-18 Advanced Micro Devices, Inc. Fabrication of a wide metal silicide on a narrow polysilicon gate structure
US7271489B2 (en) * 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US6534351B2 (en) * 2001-03-19 2003-03-18 International Business Machines Corporation Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices
US6674139B2 (en) * 2001-07-20 2004-01-06 International Business Machines Corporation Inverse T-gate structure using damascene processing
US7002223B2 (en) * 2001-07-27 2006-02-21 Samsung Electronics Co., Ltd. Semiconductor device having elevated source/drain
KR100400780B1 (ko) * 2001-12-26 2003-10-08 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6740535B2 (en) * 2002-07-29 2004-05-25 International Business Machines Corporation Enhanced T-gate structure for modulation doped field effect transistors
US6664156B1 (en) * 2002-07-31 2003-12-16 Chartered Semiconductor Manufacturing, Ltd Method for forming L-shaped spacers with precise width control
US6991973B2 (en) * 2002-09-26 2006-01-31 National Chiao Tung University Manufacturing method of thin film transistor
US6762085B2 (en) * 2002-10-01 2004-07-13 Chartered Semiconductor Manufacturing Ltd. Method of forming a high performance and low cost CMOS device
GB0230140D0 (en) * 2002-12-24 2003-01-29 Koninkl Philips Electronics Nv Thin film transistor method for producing a thin film transistor and electronic device having such a transistor
KR100635048B1 (ko) * 2003-11-25 2006-10-17 삼성에스디아이 주식회사 박막 트랜지스터, 이의 제조 방법 및 이를 사용하는 평판표시 장치
KR100576360B1 (ko) * 2003-12-08 2006-05-03 삼성전자주식회사 티형 게이트 및 엘형 스페이서를 구비하는 반도체 소자의 제조 방법
US7135372B2 (en) * 2004-09-09 2006-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon device manufacturing method
US7217647B2 (en) * 2004-11-04 2007-05-15 International Business Machines Corporation Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern
US7419879B2 (en) * 2005-01-12 2008-09-02 Samsung Electronics Co., Ltd. Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same
US7759206B2 (en) * 2005-11-29 2010-07-20 International Business Machines Corporation Methods of forming semiconductor devices using embedded L-shape spacers
US7495280B2 (en) * 2006-05-16 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with corner spacers
US9608066B1 (en) * 2015-09-29 2017-03-28 International Business Machines Corporation High-K spacer for extension-free CMOS devices with high mobility channel materials
US9853148B2 (en) * 2016-02-02 2017-12-26 Taiwan Semiconductor Manufacturing Company Ltd. Power MOSFETs and methods for manufacturing the same
CN110957349B (zh) * 2018-09-27 2023-04-07 世界先进积体电路股份有限公司 半导体装置及其制造方法
RU2693506C1 (ru) * 2018-10-22 2019-07-03 Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" Способ изготовления полупроводникового прибора
US20200227552A1 (en) * 2019-01-11 2020-07-16 Vanguard International Semiconductor Corporation Semiconductor device with dielectric neck support and method for manufacturing the same

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US4868617A (en) * 1988-04-25 1989-09-19 Elite Semiconductor & Sytems International, Inc. Gate controllable lightly doped drain mosfet devices
DE68916401T2 (de) * 1988-10-03 1994-11-17 Toshiba Kawasaki Kk Feldeffekttransistor auf einem Isolator und Verfahren zu seiner Herstellung.
JPH0734475B2 (ja) * 1989-03-10 1995-04-12 株式会社東芝 半導体装置
JPH0834313B2 (ja) * 1989-10-09 1996-03-29 株式会社東芝 半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100396895B1 (ko) * 2001-08-02 2003-09-02 삼성전자주식회사 Ｌ자형 스페이서를 채용한 반도체 소자의 제조 방법

Also Published As

Publication number Publication date
EP0490535A3 (enExample) 1994-04-06
DE69121535T2 (de) 1997-01-02
US5290720A (en) 1994-03-01
EP0490535B1 (en) 1996-08-21
DE69121535D1 (de) 1996-09-26
EP0490535A2 (en) 1992-06-17

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